Performance Enhancement in CZTS Solar Cells by SCAPS-1D Software

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Performance Enhancement in CZTS Solar Cells by SCAPS-1D

The development of CZTS-based solar cells is limited by two factors, the low open circuit voltage and the conversion efficiency. This is why, in this study, the impact of Cu2ZnSnS4 (CZTS) absorber thin layer parameters on the performance of the proposed MoS2/CZTS/CdS/ZnO heterostructure is simulated by the standard software SCAPS-1D. The improving output performances of this structure; the open circuit voltage (Voc), the short circuit current density (Jsc), the fill factor (FF) and the efficiency (h) are obtained by varying the absorber layer thickness, acceptor carrier concentration NA and taking into account the effect of the electron work function of the back metal contact. The optimized cell provides an energy conversion efficiency of 15.23% (Voc = 0.99 V, Jsc = 21.89 mA/cm2, FF = 69.79%) for an optimal thickness of 2 μm, a doping of 1×1016 cm-3. Performance enhancement of the proposed solar cell is subject to the back metal contact, the optimal simulated value of 5.7 eV of which represents that of the Platinum’s work function Pt. The interest of this simulation makes it possible to adjust the solar cells dimensions, optimize the absorbent layers doping, choose appropriately the back metal contact and therefore help to considerably reduce the various recombination phenomena as well as the secondary phases

Characterizing slow state near Si-SiO 2 in MOS structure

International audienceThe Equilibrium Voltage Step (EVS) technique has been used for extraction of depth and energy concentration profile of traps situated in the oxide of a lightly stressed metal-oxide-semiconductor (MOS) structure. This has been achieved up to the very near Si-SiO2 interface. The results are discussed and compared with those obtained using charge pumping (CP) technique. A good agreement is achieved between the trap densities extracted using the two methods even though differences in the shape of the profiles can be observed. The results also very well agree with those published previously using current deep level transient spectroscopy (C-DLTS)

Cuinse 2 Solar Cells Efficiency Optimization

Abstract In the present paper calculation of CuInSe2(CIS)/ CdS solar cell efficiency is presented. The influence of the thickness and the optical band gap of CdS and CIS layers on the solar cell performances are investigated. The thickness of CdS buffer layer, wh ich is generally neglected is taken into account. The solar cells performances calculat ions are based on the calculation, by means of developed software written with Matlab, o f photocurrent from the resolution of the well known three coupling equations: continuity equation for holes in the CdS (n -region) and fo r electrons in the CIS (p-region) and Poisson equation. The obtained results indicated that the solar cell efficiency can be improved by reducing the CdS thickness or by increasing the CIS thickness. The efficiency increasing rates are 0.01 %/ n m and 0.5 %/n m for CdS and CIS layer thickness respectively. The CdS layer alters the shorter wavelength of the solar spectrum, wh ile the CIS layer alters the longer wavelength. CIS layer optical band gap is the most crucial parameter by co mparison to the optical gap of CdS layer

FTIR and AFM studies of the Ge on Porous Silicon/Si substrate hetero-structure obtained by molecular beam epitaxy

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Investigation of microstructure and morphology for the Ge on porous silicon/Si substrate hetero-structure obtained by molecular beam epitaxy

International audienceThick porous silicon (PS) buffer layers are used as sacrificial layers to epitaxially grow planar and fully relaxed Ge membranes. The single crystal Ge layers have been deposited by molecular beam epitaxy (MBE) on PS substrate. During deposition, the pore network of PS layers has been filled with Ge. We investigate the structure and morphology of PS as fabricated and after annealing at various temperatures. We show that the PS crystalline lattice is distorted and expanded in the direction perpendicular to the substrate plane due to the presence of chemisorbed –OH. An annealing at high temperature (> 500 °C), greatly changes the PS morphology and structure. This change is marked by an increase of the pore diameter while the lattice parameter becomes tensily strained in the plane (compressed in the direction perpendicular). The morphology and structure of Ge layers are investigated by transmission electron microscopy, high resolution X-ray diffraction and atomic force microscopy as a function of the deposition temperature and deposited thickness. The results show that the surface roughness, level of relaxation and Si-Ge intermixing (Ge content) depend on the growth temperature and deposited thickness. Two sub-layers are distinguished: the layer incorporated inside the PS pores (high level of intermixing) and the layer on top of the PS surface (low level of intermixing). When deposited at temperature > 500 °C, the Ge layers are fully relaxed with a top Si1 − xGex layer x = 0.74 and a very flat surface. Such layer can serve as fully relaxed ultra-thin SiGe pseudo-substrate with high Ge content. The epitaxy of Ge on sacrificial soft PS pseudo-substrate in the experimental conditions described here provides an easy way to fabricate fully relaxed SiGe pseudo-substrates. Moreover, Ge thin films epitaxially deposited by MBE on PS could be used as relaxed pseudo-substrate in conventional microelectronic technology

Ultra-thin planar fully relaxed Ge pseudo-substrate on compliant porous silicon template layer

International audiencePorous silicon (PSi) layers are used as templates to grow epitaxial planar and fully relaxed Ge pseudo-substrates. An annealing at 600 °C, dramatically changes the PSi morphology and produces compliant template layers which serve in a second step, as substrate for the epitaxy of fully relaxed SiGe layers with a Ge content between 50% and 94%. The SiGe pseudo-substrates produced by such process exhibit a remarkable planar surface resulting from the penetration of Ge inside the pores. They could be integrated into conventional microelectronic technology for the subsequent deposition of active layers such as tensily strained Si or relaxed Ge