Adaptive RAC codes employing statistical channel evaluation

In time varying channels the noise and interference vary randomly. Forward error correction codes (FEC) on  such channels are designed to cater for the worst possible state and require a large amount of redundancy at  all time. This means that when the channel is relatively noiseless, excessive error control power and hence  redundancy is being employed and results in a reduction in the overall information rate. An adaptive encoding  technique using row and column array (RAC) codes employing a different number of parity columns that  depends on the channel state is proposed in this paper. The trellises of the proposed adaptive codes and a  statistical channel evaluation technique employing these trellises are designed and implemented.Keywords: Adaptive array codes, statistical channel evaluatio

Combined Coding And Modulation Using Runlength Limited Error Correcting Codes

Run Length Limited (RLL) codes are widely used in data transmission/storage systems, such as digital  magnetic recording and optical storage. However, they are vulnerable when used in channel transmission and  are easily corrupted by noise. Run Length Limited/Error correcting Codes (RLL/ECCs) have been designed so that they retain their original key property while being suitable for channel transmission. In this paper we  propose a Combined Coding and Modulation (CCM) scheme employing RLL/ECCs and MPSK modulation as well as RLL/ECC codes and BFSK/MPSK modulation with a view to optimise on channel bandwidth. The CCM codes and their trellis are designed and their error performances simulated in AWGN and slow Rayleigh fading  channel. The superior performance of the proposed CCM schemes is also demonstrated

A dual-stage pwm dc to ac inverter with reduced harmonic distorsion and switching losses

In conventional pulse width modulated full bridge dc to ac inverters, all power devices are switched at high  frequency and are consequently subject to significant power losses. This paper presents a modified dc to ac  inverter topology where the high frequency switching is performed by a single device in a pre-converter stage,  while the bridge switches are controlled at the low frequency of the load voltage. The proposed inverter is shown to have smaller device losses and higher power transfer efficiency than commonly used control schemes, while producing a lower harmonic distortion in the ac output voltage.Keywords: Dc to ac inverter, Pulse Width Modulatio