High Speed and Wide Bandwidth Delta-Sigma ADCs

This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CT??) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this thesis investigates excess loop delay compensation techniques at the system level which enable the design of a wide-bandwidth (BW), high-dynamic range (DR) CT?? modulator with good power-efficiency. This thesis demonstrates that CT?? ADCs implemented in nanometer CMOS are a power efficient alternative to Nyquist-rate ADCs for wide signal bandwidths (greater than 100MHz) and high dynamic ranges (more than 12-bit). The performance of a high-speed multi-bit CT?? modulator is often limited by the dynamic errors present in the feedback DAC. The applicable correction/calibration techniques are limited due to the modulator stability requirements. We have implemented a dynamic error correction technique which not only experimentally quantifies the level of dynamic errors but also improves the dynamic performance of the modulator.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

The effect of brain tomography findings on mortality in sniper shot head injuries

Objectives Penetrating gunshot head injuries have a poor prognosis and require prompt care. Brain CT is a routine component of the standard evaluation of head wounds and suspected brain injury. We aimed to investigate the effect of brain CT findings on mortality in gunshot head injury patients who were admitted to our emergency department (ED) from the Syrian Civil War

A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.Accepted Author ManuscriptElectronic Instrumentatio

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements

This paper proposes a simple digital automatic calibration method for wide-band continuous-time (CT) MASH ΣΔ ADCs. The main contribution of this method is the calibration of the errors due to the limited DC gain and 2nd pole of the loop filter integrators. The digital noise cancellation filters are calibrated by successive estimation of the DC gains and the 2nd pole, and updating the coefficients of the FIR filters. Extensive system-level and transistor-level simulations demonstrate the effectiveness and robustness of the proposed method. For an exemplary MASH ΣΔ ADC with BW of 600 MHz and SQNR of 75 dB, it can relax the DC gain requirement by 15 dB, and the 2nd pole requirement by three times, making it an enabling technique for power-efficient GHz-range ΣΔ ADC applications

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

This paper proposes both system-level and circuit-level solutions of a current-mode multi-path excess loop delay (ELD) compensation technique for continuous-time (CT) ΣΔ ADCs with multi-bit quantization and several GHz sampling rate.Thanks to the proposed solutions, the amplifier of the loop filter is not in the fast feedback (FB) loop; the delay of the pre-amplifier of the comparator is removed; and the effective regeneration time of the comparator latch is maximized. The proposed novelties enable CT ΣΔ ADCs with wide signal bandwidth and improved power efficiency. Extensive transistor-level simulations demonstrate their effectiveness and robustness. This work validates the proposed methods by transistor level design and simulations of an 8.4 GHz MASH ΣΔ ADC achieving an SNDR of 71 dB in a signal band of 600 MHz. This shows that our proposed solutions enable power-efficient multi-GHz ΣΔ ADC applications

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators

This paper reports a novel beamforming method based on Continuous Time Sigma-Delta Modulators (CT SDM) with feedforward (FF) programmable coefficients implemented as spatial FIR filters. This new method realizes analog beamforming in baseband and allows accurate beamsteering by programming banks of resistors. We present the theoretical framework and a proof-of-concept implementation as a spatio-temporal 250MHz signal bandwidth CT SDM in 40nm CMOS for a 9-channels phased array. This paper shows that the proposed method can significantly lower the ADC SNR requirements in phased-array receivers operating in the presence of multiple interferers inside the signal frequency band. Our method can enable power-efficient hybrid multi-link beam-forming when combined with the standard digital beamforming approaches

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

\u3cp\u3eThis paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.\u3c/p\u3