1,154 research outputs found

    Recent advances in biopolymeric antioxidant films and coatings for preservation of nutritional quality of minimally processed fruits and vegetables

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    Minimally processed F&V while being as fresh as the intact product, are characterized by an accelerated produce decay which affects its nutritional value during shelf-life. In this sense, food processing needs to further evolve in terms of better preservation of nutritional properties. Active packaging technology has shown positive and promising results to maintain safety and sensory properties of minimally processed F&V. This review aims to present the recent research results regarding biopolymeric antioxidant film and coating for preservation of nutritional quality of minimally processed F&V. The mechanism by which nutritional losses (around 5–30 % loss of ascorbic acid and phenolic compounds) occur from oxidation reactions in F&V and natural antioxidant have been discussed. Furthermore, regulatory aspects related to antioxidant packaging have been also reported. Biopolymers based antioxidant film and coating have been vastly used to pack F&V product. Chitosan, gelatin, casein and alginate were found to be more effective as packaging materials (both as coating and as film) to preserve the nutritional and sensory quality of F&V product. Furthermore, plant extracts (green tea and Aloe vera), essential oils (lemon grass), plant oil compounds (eugenol and citral) and phenolics (thymol) as a component of active film or coating systems have shown promising results in preserving the quality of fresh produce. The collected findings will be useful to accurately design an innovative active film or coating for nutritional quality preservation of minimally processed fresh fruits and vegetables

    Thrombin and factor Xa link the coagulation system with Liver fibrosis

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    Background: Thrombin activates hepatic stellate cells via protease-activated receptor-1. The role of Factor Xa (FXa) in hepatic fibrosis has not been elucidated. We aimed to evaluate the impact of FXa and thrombin in vitro on stellate cells and their respective inhibition in vivo using a rodent model of hepatic fibrosis. Methods: HSC-LX2 cells were incubated with FXa and/or thrombin in cell culture, stained for αSMA and relative gene expression and gel contraction calculated. C57BL/6 J mice were administered thioacetamide (TAA) for 8 weeks with Rivaroxaban (n = 15) or Dabigatran (n = 15). Control animals received TAA alone (n = 15). Fibrosis was scored and quantified using digital image analysis and hepatic tissue hydroxyproline estimated. Results Stellate cells treated with FXa and thrombin demonstrated upregulation of procollagen, TGF-beta, αSMA and significant cell contraction (43.48%+/− 4.12) compared to culturing with FXa or thrombin alone (26.90%+/− 8.90, p = 0.02; 13.1%+/− 9.84, p < 0.001). Mean fibrosis score, percentage area of fibrosis and hepatic hydroxyproline content (2.46 vs 4.08, p = 0.008; 2.02% vs 3.76%, p = 0.012; 276.0 vs 651.3, p = 0.0001) were significantly reduced in mice treated with the FXa inhibitor compared to control mice. FXa inhibition was significantly more effective than thrombin inhibition in reducing percentage area of fibrosis and hepatic hydroxyproline content (2.02% vs 3.70%,p = 0.031; 276.0 vs 413.1,p = 0.001). Conclusions: FXa promotes stellate cell contractility and activation. Early inhibition of coagulation using a FXa inhibitor significantly reduces TAA induced murine liver fibrosis and may be a viable treatment for liver fibrosis in patients

    Algorithm for Parallel Inverse Halftoning using Partitioning of Look-Up Table (LUT)

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    The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to parallelize the LUT method so that more pixels can be concurrently inverse halftoned using minimum additional hardware. The proposed algorithm partitions the single LUT of serial LUT method into N smaller Look-Up Tables (s-LUTs) such that the total number of entries in all s-LUTs remain equal to the number of entries in the single LUT of serial LUT method. The proposed algorithm can be implemented on a single FPGA (Field Programmable Gate Arrays) device with external memories to store s-LUTs

    A Parallel Algorithm for Inverse Halftoning and its Hardware

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    Lookup Table (LUT) method for inverse halftoning is computation less, fast and also yields goods results. This paper proposes a parallel algorithm for inverse halftoning by parallelizing the LUT method of inverse halftoning. The LUT method for inverse halftoning is parallelized by dividing the single Look-Up Table of LUT method for inverse halftoning into many smaller Look-up Tables (sLUTs). In the parallel algorithm up-to four pixels can be fetched from the halftone image concurrently and go to their separate smaller Look-Up Tables (sLUT) from where each template fetches its inverse halftone value independent to other pixels. The parallelization can increase the speed of inverse halftoning by up-to 4 times while the total entries in all smaller Look-Up Tables (sLUTs) remains equal to the entries in the single LUT of LUT method for inverse halftoning. Some degradation in image quality is noticed due to parallelization. The complete implementation of the method takes two CPLD devices with external content addressable memories (CAM) and static RAMs to store sLUTs

    Parallel Algorithms for Look-Up Table (LUT) Inverse Haldtoning

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    The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose six algorithms to parallelize the LUT method so that more pixels can be concurrently inverse halftone using minimum additional hardware. The proposed algorithms partition the single LUT of serial LUT method into N smaller Look-Up Tables (s − LUTs) such that the total number of contents in all s−LUTs remain equal to the number of contents in the single LUT of serial LUT method. The proposed parallel algorithms have image quality equal to the serial LUT method when gain in clock cycles over the serial method is less and have lesser image quality comparetively to serial LUT method when gain in clock cycles over the serial method is very high. The parallel algorithms can be implemented on FPGA (Field Programmable Gate Arrays) devices with external CAM (Content Addressable Memories) and ROM (Read Only Memories)

    Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning

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    Look-Up Table (LUT) method for inverse halftoning is computation less, fast, and also yields goods results. It employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that can perform parallel inverse halftone operation by partitioning the single LUT into N smaller Look-Up Tables (s-LUTs). Thereby, upto k (k≤N) pixels can be concurrently fetched from the halftone image, and their contone values can also be fetched concurrently from separate smaller Look-Up Tables (s-LUT). The parallelization increases the speed of inverse halftoning by upto k times while the total entries in all s-LUTs remains equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is due to some contone values cannot be fetched in the same cycle because some other contone value is being fetched from the s-LUT. The complete implementation of the algorithm requires two CPLD devices for computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs

    Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning

    Get PDF
    Look-Up Table (LUT) method for inverse halftoning is computation less, fast, and also yields goods results. It employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that can perform parallel inverse halftone operation by partitioning the single LUT into N smaller Look-Up Tables (s-LUTs). Thereby, upto k (k≤N) pixels can be concurrently fetched from the halftone image, and their contone values can also be fetched concurrently from separate smaller Look-Up Tables (s-LUT). The parallelization increases the speed of inverse halftoning by upto k times while the total entries in all s-LUTs remains equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is due to some contone values cannot be fetched in the same cycle because some other contone value is being fetched from the s-LUT. The complete implementation of the algorithm requires two CPLD devices for computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs

    Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning

    Get PDF
    Look-Up Table (LUT) method for inverse halftoning is computation less, fast, and also yields goods results. It employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that can perform parallel inverse halftone operation by partitioning the single LUT into N smaller Look-Up Tables (s-LUTs). Thereby, upto k (k≤N) pixels can be concurrently fetched from the halftone image, and their contone values can also be fetched concurrently from separate smaller Look-Up Tables (s-LUT). The parallelization increases the speed of inverse halftoning by upto k times while the total entries in all s-LUTs remains equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is due to some contone values cannot be fetched in the same cycle because some other contone value is being fetched from the s-LUT. The complete implementation of the algorithm requires two CPLD devices for computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs

    Parallel Inverse Halftoning by Look-Up Table (LUT) Partitioning

    Get PDF
    Look-Up Table (LUT) method for inverse halftoning is computation less, fast, and also yields goods results. It employs a single LUT that is stored in a ROM and contains pre-computed contone (gray level) values for inverse halftone operation. This paper proposes an algorithm that can perform parallel inverse halftone operation by partitioning the single LUT into N smaller Look-Up Tables (s-LUTs). Thereby, upto k (k≤N) pixels can be concurrently fetched from the halftone image, and their contone values can also be fetched concurrently from separate smaller Look-Up Tables (s-LUT). The parallelization increases the speed of inverse halftoning by upto k times while the total entries in all s-LUTs remains equal to the entries in the single LUT of the serial LUT method. Some degradation in image quality is possible due to pixel loss during parallel fetching. This is due to some contone values cannot be fetched in the same cycle because some other contone value is being fetched from the s-LUT. The complete implementation of the algorithm requires two CPLD devices for computational portion, external content addressable memories (CAM) and static RAMs to store s-LUTs

    Algorithm for Parallel Inverse Halftoning using Partitioning of Look-Up Table (LUT)

    Get PDF
    The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to parallelize the LUT method so that more pixels can be concurrently inverse halftoned using minimum additional hardware. The proposed algorithm partitions the single LUT of serial LUT method into N smaller Look-Up Tables (s-LUTs) such that the total number of entries in all s-LUTs remain equal to the number of entries in the single LUT of serial LUT method. The proposed algorithm can be implemented on a single FPGA (Field Programmable Gate Arrays) device with external memories to store s-LUTs
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