The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to parallelize the LUT method so that more pixels can be concurrently inverse halftoned using minimum additional hardware. The proposed algorithm partitions the single LUT of serial LUT method into N smaller Look-Up Tables (s-LUTs) such that the total number of entries in all s-LUTs remain equal to the number of entries in the single LUT of serial LUT method. The proposed algorithm can be implemented on a single FPGA (Field Programmable Gate Arrays) device with external memories to store s-LUTs
