Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)

In this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics

The technology and healthcare industries have been deeply intertwined for quite some time. New opportunities, however, are now arising as a result of fast-paced expansion in the areas of the Internet of Things (IoT) and Big Data. In addition, as people across the globe have begun to adopt wearable biosensors, new applications for individualized eHealth and mHealth technologies have emerged. The upsides of these technologies are clear: they are highly available, easily accessible, and simple to personalize; additionally they make it easy for providers to deliver individualized content cost-effectively, at scale. At the same time, a number of hurdles currently stand in the way of truly reliable, adaptive, safe and efficient personal healthcare devices. Major technological milestones will need to be reached in order to address and overcome those hurdles; and that will require closer collaboration between hardware and software developers and medical personnel such as physicians, nurses, and healthcare workers. The purpose of this special issue is to analyze the top concerns in IoT technologies that pertain to smart sensors for health care applications; particularly applications targeted at individualized tele-health interventions with the goal of enabling healthier ways of life. These applications include wearable and body sensors, advanced pervasive healthcare systems, and the Big Data analytics required to inform these devices

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1–5 GHz band of the UWB FCC spectrum mask on channels of 500MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs,and a clock generation network. The receiver is implemented in 0.18um CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate