CMOS OTA-C high-frequency sinusoidal oscillators

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3- and 2- mu m CMOS (MOSIS) prototypes that exhibit oscillation frequencies of up to 69 MHz are obtained. The amplitudes can be adjusted between 1 V peak to peak and 100 mV peak to peak. Total harmonic distortions from 2.8% down to 0.2% have been measured experimentally.Comisión Interministerial de Ciencia y Tecnología ME87-000

On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.Comisión Interministerial de Ciencia y Tecnología ME87-000

VLSI implementation of a transconductance mode continuous BAM with on chip learning and dynamic analog memory

In this paper we present a complete VLSI Continuous-Time Bidirectional Associative Memory (BAM). The short term memory (STM) section is implemented using small transconductance four quadrant multipliers, and capacitors for the integrators. The long term memory (LTM) is built using an additional multiplier that uses locally available signals to perform Hebbian learning. The value of the learned weight is present at a capacitor for each synapse. After learning has been accomplished the value of the stored weight voltage can be refreshed using a simple AID-D/A conversion, which if done fast enough, will maintain the weight value within a discrete interval of the complete weight range. Such a discretization still allows good performance of the STM section after learning is finished

Hysteresis based neural oscillators for VLSI implementations

The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible models to perform the desired tasks. This yields to the use of sigmoidal type neurons that have a static input-output relationship. However, in some cases, especially when the research is close to biological neuron systems emulation, such simplifled models are not always valid. In these cases, a neuron model closer to biological neurons is needed, namely the oscillatory neuron [l-41. For these neurons, when they are active, their output is a sequence of pulses. In this paper we present several circuits that can be set in an active state to yield an oscillatory output. The difference between the circuits is based on whether the output has two unique output states (off, or on flring at a specific frequency), or has a continuum between the on and off states so t h a t the output frequency changes sigmoidally between zero and its maximum

Frequency tuning loop for VCOs

A frequency tuning circuit is introduced for VCOs (voltage-controlled oscillators) so that the final relationship between oscillating frequency and input control voltage is fixed and independent of nonidealities. This tuning loop is applied to an OTA-C sinusoidal VCO. Such an oscillator has an output frequency-input voltage relationship that depends on temperature, process parameters, and even amplitude of the oscillations. It is shown that, by adding the tuning loop, nonideal dependences will be minimized

Very high frequency CMOS OTA-C quadrature oscillators

An approach to the design of high-frequency monolithic voltage-controlled oscillators using operational transconductance amplifiers and capacitors is given. Results from two 3 μm CMOS prototypes are presented. Both frequency and amplitude of the oscillations can be tuned by means of control voltages. Programmable oscillator frequencies up to 56.1 MHz are obtained, and the amplitudes are adjustable between 1 V peak-to-peak and 100 mV peak-to-peak. Total harmonic distortions from 2.8% down to 0.2% were experimentally measured

A modular T-mode design approach for analog neural network hardware implementations

A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART1 network, or a constrained optimization network. Experimentally measured results from CMOS 2-μm double-metal, double-polysilicon prototypes (MOSIS) are presented

A Programmable Neural Oscillator Cell

A programmable analog neural oscillator cell architecture is presented. The proposed neuron circuit is of hysteretic neural nature with its implementation based on operational transconductance amplifiers (OTA's). The hysteresis loop as well as the frequency of oscillation are voltage (or current) dependent. The architecture, which involves two OTA's, a current mirror, a capacitor, a diode, and a resistor is very suitable for monolithic integrated circuits. Experimental results confirm the expected flexibility of the synthetic neuron

A CMOS Implementation of Fitzhugh-Nagumo Neuron Model

A CMOS circuit is proposed that emulates FitzHugh-Nagumo's differential equations using OTAs, diode connected MOSFETs and capacitors. These equations model the fundamental behavior of biological neuron cells. Fitz- Hugh-Nagumo's model is characterized by two threshold values. If the input to the neuron is between the two thresholds the output yields a sequence of firing pulses, if the input is outside this range, no output is observed. The resulting circuit due to the (voltage) programmability of the OTA allows one to easily vary parameters. Thus a large family of solutions can be obtained including the Van der Pol's equation. Experimental results from a CMOS prototype are given that show the suitability of the technique used, and their potential for biological CMOS system emulation

Analog neural networks for real-time constrained optimization

Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, programmability, and reconfigurability. A general architecture for minimizing piecewise functions by using gradient schemes is introduced. Switched-capacitor (SC) building blocks featuring improved characteristics in terms of area occupation and operation speed are presented. The implementation of the architectures by using the newest switched-current techniques is discussed. The layout of a 3-μm CMOS SC prototype for a quadratic optimization problem with linear constraints is given