High frequency CMOS amplifier with improved linearity

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved

Circularly symmetric algorithm for UWB RF signal receiving channel based on noise cancellation

Due to the high redundancy of ultra-wideband (UWB) radio frequency (RF) signal receiving channel and the channel’s non-rotation invariance, the signal-to-noise ratio (SNR) of signal transmission is increased. In order to solve this problem, a circularly symmetric algorithm for the UWB RF signal receiving channel based on spectrum compression cannot effectively reduce the redundancy of UWB RF signal receiving channel; the channel does not have rotation invariance; and the effect of noise reduction is poor. A circularly symmetric algorithm for the UWB RF signal receiving channel based on noise cancellation is proposed, and a noise cancellation structure at the input stage of the receiving channel is constructed to ensure channel noise cancellation and reduce noise in the channel. On this basis, five power zones are used to reasonably select RF devices, receive and downconvert UWB RF signal receiving channel, and convert the received UWB RF signal channel into circular symmetric Gabor transform to reduce redundancy and ensure the strict rotation invariance of the channel. The experimental results show that the proposed algorithm guarantees the quality of the signal and the stable transmission of the signal information. The SNR is 3.8672, and the root mean square error is 0.4078. The third-order cross-modulation coefficient of the signal receiving channel controlled by the algorithm meets the requirements of the index and the mirror frequency rejection requirement of the index

Locatable-Body Temperature Monitoring Based on Semi-Active UHF RFID Tags

This paper presents the use of radio-frequency identification (RFID) technology for the real-time remote monitoring of body temperature, while an associated program can determine the location of the body carrying the respective sensor. The RFID chip’s internal integrated temperature sensor is used for both the human-body temperature detection and as a measurement device, while using radio-frequency communication to broadcast the temperature information. The adopted RFID location technology makes use of reference tags together with a nearest neighbor localization algorithm and a multiple-antenna time-division multiplexing location system. A graphical user interface (GUI) was developed for collecting temperature and location data for the data fusion by using RFID protocols. With a puppy as test object, temperature detection and localization experiments were carried out. The measured results show that the applied method, when using a mercury thermometer for comparison in terms of measuring the temperature of the dog, has a good consistency, with an average temperature error of 0.283 °C. When using the associated program over the area of 12.25 m2, the average location error is of 0.461 m, which verifies the feasibility of the sensor-carrier location by using the proposed program

Monolithically Integrated Optoelectronic Receivers Implemented in 0. 25μm MS/RF CMOS

A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC

Two-Element Tapered Slot Antenna Array for Terahertz Resonant Tunneling Diode Oscillators

Two-element tapered slot antenna (TSA) array for terahertz (THz) resonant tunneling diode (RTD) oscillators is proposed in this paper. The proposed TSA array has the advantages of both the high directivity and high gain at the horizontal direction and hence can facilitate the horizontal communication between the RTD oscillators and other integrated circuit chips. A MIM (metal-insulator-metal) stub with a T-shaped slot is used to reduce the mutual coupling between the TSA elements. The validity and feasibility of the proposed TSA array have been simulated and analyzed by the ANSYS/ANSOFT’s High Frequency Structure Simulator (HFSS). Detailed modeling approaches and theoretical analysis of the proposed TSA array have been fully addressed. The simulation results show that the mutual coupling between the TSA elements is reduced below −40 dB. Furthermore, at 500 GHz, the directivity, the gain, and the half power beam width (HPBW) at the E-plane of the proposed TSA array are 12.18 dB, 13.09 dB, and 61°, respectively. The proposed analytical method and achieved performance are very promising for the antenna array integrated with the RTD oscillators at the THz frequency and could pave the way to the design of the THz antenna array for the RTD oscillators

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s

Bandwidth Design for CMOS Monolithic Photoreceiver

A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade(RGC) transimpedance amplifier (TIA) is designed. The small signal circuit model of DPD is given and the band width design method of a monolithic photoreceiver is presented. An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail. A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0. 6um CMOS process and the test result is given