A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature

Significance of Logic Synthesis in FPGA-Based Design of Image and Signal Processing Systems

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, application of the functional decomposition-based method to LUT blocks optimization, and mapping has been investigated. The chapter presents results of the comparison of various design approaches in these areas

A New Approach to a FSM Implementation in Embedded Memory Blocks of FPGA Devices with Use of the Functional Decomposition

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Implementation of Large Neural Networks Using Decomposition

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder

An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic

Efficient input support selection for sub-functions in functional decomposition based on information relationship measures

Functional decomposition has important applications in many fields of modern engineering and science, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, databases, data mining etc. However, its practical usefulness for very complex systems is limited by the lack of an effective and efficient method for selection of the appropriate input support for sub-systems. A classical method based on a systematic search of the whole solution space is inefficient. In this paper, an effective and efficient heuristic method for input support selection is proposed and discussed. The method is based on the application of information relationship measures, which allows us to reduce the search space to a manageable size while keeping high-quality solutions in the reduced space. The experimental results demonstrate that the proposed heuristic method is able to construct optimal or near optimal support very efficiently even for large systems. It is much faster than the systematic method while delivering results of comparable quality

Functional Decomposition and its Applications in Design of Digital Circuits and Machine Learning

In this paper, we will begin with an overview of functional decomposition algorithms based on different graph coloring heuristics. We will then discuss the applications of decomposition strategy for the computer aided design of digital circuits and for the supervised learning of neural networks. While decomposition was used successfully in logic synthesis for several years, its application in the area of neural networks is a novel and promising approach. The computer experiments will show significant benefits in mini mization of silicon space required for digital circuit implementation as well as in reduction of training time for neural networks

Technology driven multilevel logic synthesis based on functional decomposition into gates

In this paper a new method is proposed for multilevel logic synthesis based on functional decomposition into gates. Unlike the traditional approach to the decomposition, where the basic components of the decomposition network are the universal cells, we propose a method, which instead of cells uses gates, but preserves advantages of the functional decomposition. This approach makes possible to improve traditional FPGA functional decomposition onto the more general algorithm, which is also useful for other technologies in VLSI ASIC design

Reduction of Knowledge Representation Using Logic Minimization Techniques

This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented

Technology driven multilevel logic synthesis based on functional decomposition into gates

\u3cp\u3eIn this paper a new method is proposed for multilevel logic synthesis based on functional decomposition into gates. Unlike the traditional approach to the decomposition, where the basic components of the decomposition network are the universal cells, we propose a method, which instead of cells uses gates, but preserves advantages of the functional decomposition. This approach makes possible to improve traditional FPGA functional decomposition onto the more general algorithm, which is also useful for other technologies in VLSI ASIC design.\u3c/p\u3