8,500 research outputs found
Enhancing microRNA167A expression in seed decreases the α-linolenic acid content and increases seed size in Camelina sativa.
Despite well established roles of microRNAs in plant development, few aspects have been addressed to understand their effects in seeds especially on lipid metabolism. In this study, we showed that overexpressing microRNA167A (miR167OE) in camelina (Camelina sativa) under a seed-specific promoter changed fatty acid composition and increased seed size. Specifically, the miR167OE seeds had a lower α-linolenic acid with a concomitantly higher linoleic acid content than the wild-type. This decreased level of fatty acid desaturation corresponded to a decreased transcriptional expression of the camelina fatty acid desaturase3 (CsFAD3) in developing seeds. MiR167 targeted the transcription factor auxin response factor (CsARF8) in camelina, as had been reported previously in Arabidopsis. Chromatin immunoprecipitation experiments combined with transcriptome analysis indicated that CsARF8 bound to promoters of camelina bZIP67 and ABI3 genes. These transcription factors directly or through the ABI3-bZIP12 pathway regulate CsFAD3 expression and affect α-linolenic acid accumulation. In addition, to decipher the miR167A-CsARF8 mediated transcriptional cascade for CsFAD3 suppression, transcriptome analysis was conducted to implicate mechanisms that regulate seed size in camelina. Expression levels of many genes were altered in miR167OE, including orthologs that have previously been identified to affect seed size in other plants. Most notably, genes for seed coat development such as suberin and lignin biosynthesis were down-regulated. This study provides valuable insights into the regulatory mechanism of fatty acid metabolism and seed size determination, and suggests possible approaches to improve these important traits in camelina
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Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel
High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain
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