Street Viewer: An Autonomous Vision Based Traffic Tracking System

The development of intelligent transportation systems requires the availability of both accurate traffic information in real time and a cost-effective solution. In this paper, we describe Street Viewer, a system capable of analyzing the traffic behavior in different scenarios from images taken with an off-the-shelf optical camera. Street Viewer operates in real time on embedded hardware architectures with limited computational resources. The system features a pipelined architecture that, on one side, allows one to exploit multi-threading intensively and, on the other side, allows one to improve the overall accuracy and robustness of the system, since each layer is aimed at refining for the following layers the information it receives as input. Another relevant feature of our approach is that it is self-adaptive. During an initial setup, the application runs in learning mode to build a model of the flow patterns in the observed area. Once the model is stable, the system switches to the on-line mode where the flow model is used to count vehicles traveling on each lane and to produce a traffic information summary. If changes in the flow model are detected, the system switches back autonomously to the learning mode. The accuracy and the robustness of the system are analyzed in the paper through experimental results obtained on several different scenarios and running the system for long periods of time

Internal Guidelines for Reducing Lymph Node Contour Variability in Total Marrow and Lymph Node Irradiation

Background: The total marrow and lymph node irradiation (TMLI) target includes the bones, spleen, and lymph node chains, with the latter being the most challenging structures to contour. We evaluated the impact of introducing internal contour guidelines to reduce the inter- and intraobserver lymph node delineation variability in TMLI treatments. Methods: A total of 10 patients were randomly selected from our database of 104 TMLI patients so as to evaluate the guidelines' efficacy. The lymph node clinical target volume (CTV_LN) was recontoured according to the guidelines (CTV_LN_GL_RO1) and compared to the historical guidelines (CTV_LN_Old). Both topological (i.e., Dice similarity coefficient (DSC)) and dosimetric (i.e., V95 (the volume receiving 95% of the prescription dose) metrics were calculated for all paired contours. Results: The mean DSCs were 0.82 ± 0.09, 0.97 ± 0.01, and 0.98 ± 0.02, respectively, for CTV_LN_Old vs. CTV_LN_GL_RO1, and between the inter- and intraobserver contours following the guidelines. Correspondingly, the mean CTV_LN-V95 dose differences were 4.8 ± 4.7%, 0.03 ± 0.5%, and 0.1 ± 0.1%. Conclusions: The guidelines reduced the CTV_LN contour variability. The high target coverage agreement revealed that historical CTV-to-planning-target-volume margins were safe, even if a relatively low DSC was observed

Impact of the Extremities Positioning on the Set-Up Reproducibility for the Total Marrow Irradiation Treatment

Total marrow (lymph node) irradiation (TMI/TMLI) delivery requires more time than standard radiotherapy treatments. The patient's extremities, through the joints, can experience large movements. The reproducibility of TMI/TMLI patients' extremities was evaluated to find the best positioning and reduce unwanted movements. Eighty TMI/TMLI patients were selected (2013-2022). During treatment, a cone-beam computed tomography (CBCT) was performed for each isocenter to reposition the patient. CBCT-CT pairs were evaluated considering: (i) online vector shift (OVS) that matched the two series; (ii) residual vector shift (RVS) to reposition the patient's extremities; (iii) qualitative agreement (range 1-5). Patients were subdivided into (i) arms either leaning on the frame or above the body; (ii) with or without a personal cushion for foot positioning. The Mann-Whitney test was considered (p < 0.05 significant). Six-hundred-twenty-nine CBCTs were analyzed. The median OVS was 4.0 mm, with only 1.6% of cases ranked < 3, and 24% of RVS > 10 mm. Arms leaning on the frame had significantly smaller RVS than above the body (median: 8.0 mm/6.0 mm, p < 0.05). Using a personal cushion for the feet significantly improved the RVS than without cushions (median: 8.5 mm/1.8 mm, p < 0.01). The role and experience of the radiotherapy team are fundamental to optimizing the TMI/TMLI patient setup

Algorithm Optimization and Applications for Embedded Systems

Optimizations for Embedded Systems imply ad-hoc tunings and performance improvements, as well as development of specific algorithms and data structures, well suited for embedded platforms. This work first focuses on efficient and accurate implementation of visual search algorithms on embedded GPUs adopting the OpenGL ES and OpenCL languages. Considering embedded GPUs that support only low precision computations, we discuss the problems arising during the design phase, and we detail our implementation choices, focusing on two well-known key-point detectors SIFT and ALP. We illustrate how to re-engineering standard Gaussian Scale Space computations to mobile multi-core parallel GPUs using the OpenGL ES language transforming standard, i.e., single (or double) precision floating-point computations, to reduced-precision GPU arithmetic without precision loss. We also concentrate on an efficient and accurate OpenCL implementation of the main MPEG Compact Descriptors for Visual Search (CDVS) stages. We introduce new techniques to adapt sequential algorithms to parallel processing. Furthermore, to reduce the memory accesses, and efficiently distribute the OpenCL kernels workload, we use new approaches to store and retrieve CDVS information on proper GPU data structures. Secondly, we focus on improving the scalability of formal verification algorithms for Embedded System design models. We address the problem of reducing the size of Craig interpolants generated within inner steps of SAT-based Unbounded Model Checking. Craig interpolants are obtained from refutation proofs of unsatisfiable SAT runs, in terms of and/or circuits of linear size, w.r.t. the proof. We also consider the issue of property grouping, property decomposition, and property coverage in model checking problems. Property grouping, i.e., clustering, is a valuable solution whenever (very) large sets of properties have to be proven for a given model. On the other hand, property decomposition can be effective whenever a given property turns-out (or it is expected) to be “hard-to-prove”. Overall, experimental results are promising and demonstrate that our solutions have a speed-up over the existing ones and can be really beneficial if appropriately integrated in a new environment

Algorithm Optimization and Applications for Embedded Systems

Optimizations for Embedded Systems imply ad-hoc tunings and performance improvements, as well as development of specific algorithms and data structures, well suited for embedded platforms. This work first focuses on efficient and accurate implementation of visual search algorithms on embedded GPUs adopting the OpenGL ES and OpenCL languages. Considering embedded GPUs that support only low precision computations, we discuss the problems arising during the design phase, and we detail our implementation choices, focusing on two well-known key-point detectors SIFT and ALP. We illustrate how to re-engineering standard Gaussian Scale Space computations to mobile multi-core parallel GPUs using the OpenGL ES language transforming standard, i.e., single (or double) precision floating-point computations, to reduced-precision GPU arithmetic without precision loss. We also concentrate on an efficient and accurate OpenCL implementation of the main MPEG Compact Descriptors for Visual Search (CDVS) stages. We introduce new techniques to adapt sequential algorithms to parallel processing. Furthermore, to reduce the memory accesses, and efficiently distribute the OpenCL kernels workload, we use new approaches to store and retrieve CDVS information on proper GPU data structures. Secondly, we focus on improving the scalability of formal verification algorithms for Embedded System design models. We address the problem of reducing the size of Craig interpolants generated within inner steps of SAT-based Unbounded Model Checking. Craig interpolants are obtained from refutation proofs of unsatisfiable SAT runs, in terms of and/or circuits of linear size, w.r.t. the proof. We also consider the issue of property grouping, property decomposition, and property coverage in model checking problems. Property grouping, i.e., clustering, is a valuable solution whenever (very) large sets of properties have to be proven for a given model. On the other hand, property decomposition can be effective whenever a given property turns-out (or it is expected) to be “hard-to-prove”. Overall, experimental results are promising and demonstrate that our solutions have a speed-up over the existing ones and can be really beneficial if appropriately integrated in a new environment

Optimization techniques for craig interpolant compaction in unbounded model checking

This paper addresses the problem of reducing the size of Craig interpolants generated within inner steps of SAT-based Unbounded Model Checking. Craig interpolants are obtained from refutation proofs of unsatisfiable SAT runs, in terms of and/or circuits of linear size, w.r.t. the proof. Existing techniques address proof reduction, whereas interpolant circuit compaction is typically considered as an implementation problem, tackled with standard logic synthesis techniques. We propose a three step interpolant computation process, specifically oriented to scalability, in which we: (1) exploit an existing technique to detect and remove redundancies in refutation proofs, (2) apply customized light weight combinational logic reductions (constant propagation, ODC-based implifications, and BDD-based sweeping) directly on the proof graph data structure, (3) introduce an ad-hoc combinational reduction procedure for large interpolant circuits, based on the incrementality and divide-and-conquer paradigms. The main contributions of our approach are represented by the overall approach, the proposed combinational reduction technique, and a detailed experimental evaluation of the interpolant generation process, on a set of benchmarks from the Hardware Model Checking Competitions 2013 and 201

Optimization techniques for Craig Interpolant compaction in Unbounded Model Checking

This paper addresses the problem of reducing the size of Craig interpolants generated within inner steps of SAT-based Unbounded Model Checking. Craig interpolants are obtained from refutation proofs of unsatisfiable SAT runs, in terms of and/or circuits of linear size, w.r.t. the proof. Existing techniques address proof reduction, whereas interpolant com- paction is typically considered as an implementation problem, tackled using standard logic synthesis techniques. We propose an integrated three step process, in which we: (1) exploit an existing technique to detect and remove redundancies in refutation proofs, (2) apply combinational logic reductions (constant propagation, ODC-based simplifications, and BDD-based sweeping) directly on the proof graph data structure, (3) eventually apply ad hoc combinational logic synthesis steps on interpolant circuits. The overall procedure is novel (as well as parts of the above listed steps), and represents an advance w.r.t. the state-of-the art. The paper includes an experimental evaluation, showing the benefits of the proposed technique, on a set of benchmarks from the Hardware Model Checking Competition 2011

Optimization techniques for Craig Interpolant compaction in Unbounded Model Checking

This paper addresses the problem of reducing the size of Craig interpolants generated within inner steps of SAT-based Unbounded Model Checking. Craig interpolants are obtained from refutation proofs of unsatisfiable SAT runs, in terms of and/or circuits of linear size, w.r.t. the proof. Existing techniques address proof reduction, whereas interpolant com- paction is typically considered as an implementation problem, tackled using standard logic synthesis techniques. We propose an integrated three step process, in which we: (1) exploit an existing technique to detect and remove redundancies in refutation proofs, (2) apply combinational logic reductions (constant propagation, ODC-based simplifications, and BDD-based sweeping) directly on the proof graph data structure, (3) eventually apply ad hoc combinational logic synthesis steps on interpolant circuits. The overall procedure is novel (as well as parts of the above listed steps), and represents an advance w.r.t. the state-of-the art. The paper includes an experimental evaluation, showing the benefits of the proposed technique, on a set of benchmarks from the Hardware Model Checking Competition 2011

CDVS feature selection on embedded systems

Mobile image retrieval and pairwise matching applications pose a unique set of challenges. As communicating large amount of data could take tens of seconds over a slow wireless link, MPEG defined the CDVS standard to transfer over the network only the data essential to the matching, and not the entire image. However, the extraction of salient image features is a very time consuming process, and it may still require times in the order of seconds when running on CPU of modern mobile devices. To reduce feature extraction computation times, we re-design the MPEG-CDVS feature selection algorithm for highly parallel embedded GPUs. We consider two different approaches compliant to the standard. In the first one, feature selection is performed before the orientation assignment stage. In the second one, it is performed after. We present a complete experimental analysis on a large test set. Our experiments show that our GPU-based approaches are remarkably faster than the CPU-based reference implementation of the standard, while maintaining a comparable precision in terms of true and false positive rates. To sum up, our solutions have been proved to be effective for real-time applications running on modern embedded systems

Efficient Complex High-Precision Computations on GPUs without Precision Loss

General-purpose computing on graphics processing units is the utilization of a graphics processing unit (GPU) to perform computation in applications traditionally handled by the central processing unit. Many attempts have been made to implement well-known algorithms on embedded and mobile GPUs. Unfortunately, these applications are computationally complex and often require high precision arithmetic, whereas embedded and mobile GPUs are designed speci ̄cally for graphics, and thus are very restrictive in terms of input/output, precision, programming style and primitives available. This paper studies how to implement effcient and accurate high-precision algorithms on embedded GPUs adopting the OpenGL ES language. We discuss the problems arising during the design phase, and we detail our implementation choices, focusing on the SIFT and ALP key-point detectors. We transform standard, i.e., single (or double) precision floating-point computations, to reduced-precision GPU arithmetic without precision loss. We develop a desktop framework to simulate Gaussian Scale Space transforms on all possible target embedded GPU platforms, and with all possible range and precision arithmetic. We illustrate how to re-engineer standard Gaussian Scale Space computations to mobile multi-core parallel GPUs using the OpenGL ES language. We present experiments on a large set of standard images, proving how efficiency and accuracy can be maintained on different target platforms. To sum up, we present a complete framework to minimize future programming effort, i.e., to easily check, on different embedded platforms, the accuracy and performance of complex algorithms requiring high-precision computations