Study on advanced information processing system

Issues related to the reliability of a redundant system with large main memory are addressed. In particular, the Fault-Tolerant Processor (FTP) for Advanced Launch System (ALS) is used as a basis for our presentation. When the system is free of latent faults, the probability of system crash due to nearly-coincident channel faults is shown to be insignificant even when the outputs of computing channels are infrequently voted on. In particular, using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs--with a low hardware overhead--can be used to reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, we have developed two schemes, called Scheme 1 and Scheme 2, to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter

Study on fault-tolerant processors for advanced launch system

Issues related to the reliability of a redundant system with large main memory are addressed. The Fault-Tolerant Processor (FTP) for the Advanced Launch System (ALS) is used as a basis for the presentation. When the system is free of latent faults, the probability of system crash due to multiple channel faults is shown to be insignificant even when voting on the outputs of computing channels is infrequent. Using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing redundancy or the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by those CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs (with a very low hardware overhead) can be used to dramatically reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, two different schemes were developed to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter

Fastplay-A Parallelization Model and Implementation of SMC on CUDA based GPU Cluster Architecture

We propose a four-tiered parallelization model for acceleration of the secure multiparty computation (SMC) on the CUDA based Graphic Processing Unit (GPU) cluster architecture. Specification layer is the top layer, which adopts the SFDL of Fairplay for specification of secure computations. The SHDL file generated by the SFDL compiler of Fairplay is used as inputs to the function layer, for which we developed both multi-core and GPU based control functions for garbling of various types of Boolean gates, and ECC-based 1-out-of-2 Oblivious Transfer (OT). These high level control functions invoke computation of 3-DGG (3-DES gate garbling), EGG (ECC based gate garbling), and ECC based OT that run at the secure protocol layer. An ECC Arithmetic GPU Library (EAGL), which co-run on the GPU cluster and its host, manages utilization of GPUs in parallel computing of ECC arithmetic. Experimental results show highly linear acceleration of ECC related computations when the system is not overloaded; When running on a GPU cluster consisted of 6 Tesla C870 devices, with GPU devices fully loaded with over 3000 execution threads, Fastplay achieved 35~40 times of acceleration over a serial implementation running on a 2.53GHz duo core CPU and 4GB memory. When the execution thread count exceeds this number, the speed up factor remains fairly constant, yet slightly increased

Privacy-Preserving Matching Protocols for Attributes and Strings

In this technical report we present two new privacy-preserving matching protocols for singular attributes and strings, respectively. The first one is used for matching of common attributes without revealing unmatched ones to each other. The second protocol is used to discover the longest common sub-string of two input strings in a privacy-preserving manner. Compared with previous work, our solutions are efficient and suitable to implement for many different applications, e.g., discovery of common worm signatures, computation of similarity of IP payloads

High performance and high reliability multistage interconnection networks.

New architectures to improve the performance and reliability of multistage interconnection networks (MINs) are proposed and analyzed in this dissertation. To improve the system performance, a cost-effective technique called network overlapping and memory interleaving (NOMI) is first developed. In the NOMI technique, the network blocking probability is decreased by using larger switches, and the network utilization is increased by overlapping operations on the network and memory modules. A branch and bound procedure is developed to optimize the system throughput, system cost and the mean system waiting time. Network reliability is improved by a two-level testing method called the polynomial testing method. In the polynomial testing method, two easily-testable architectures are developed to support the high-level testing strategy and the low-level testing strategy. The latter can test the network off-line in a very short time period, whereas the former is a concurrent testing strategy which tests a subset of system components at a time to locate most functional faults from the output of the path under test. In the high-level testing strategy, one or two paths need to be locked up for testing at a time. Packets will be blocked if they must traverse through the locked path. If a path is locked up too long, packets will be blocked at all the possible source nodes of the locked path, thereby forming a congestion tree. The probability distribution of the time to block an arbitrary node under the high-level testing is derived, and the mean time to dissipate congestion trees is determined via simulation. A long testing procedure is decomposed into smaller batches, and the optimal batch size is derived to minimize the performance loss by the high-level testing. Since fault coverage is a non-decreasing function of the length of test pattern, optimal fault coverages are derived for different levels of testing difficulty to balance the cost of undetectable faults and the cost of mean fault detection time of detectable faults.Ph.D.Computer scienceUniversity of Michiganhttp://deepblue.lib.umich.edu/bitstream/2027.42/162221/1/8920578.pd

Design and Testing of a CPU Emulator Design and Testing of a CPU Emulator

Abstrac