GaAs:Mn nanowires grown by molecular beam epitaxy of (Ga,Mn)As at MnAs segregation conditions

GaAs:Mn nanowires were obtained on GaAs(001) and GaAs(111)B substrates by molecular beam epitaxial growth of (Ga,Mn)As at conditions leading to MnAs phase separation. Their density is proportional to the density of catalyzing MnAs nanoislands, which can be controlled by the Mn flux and/or the substrate temperature. Being rooted in the ferromagnetic semiconductor (Ga,Mn)As, the nanowires combine one-dimensional properties with the magnetic properties of (Ga,Mn)As and provide natural, self assembled structures for nanospintronics.Comment: 13 pages, 6 figure

Modeling the effects of lanthanum, nitrogen, and fluorine treatments of Si-SiON-HfO2-TiN gate stacks in 28 nm high-k-metal gate technology

We have carried out a combined experimental and theoretical study on the influence of lanthanum, nitrogen, and fluorine treatments on the electric properties of high-k metal gate (HKMG) devices. In particular, we have developed a theoretical gate stack model which is able to predict qualitatively and quantitatively the influence of nitrogen, fluorine, and lanthanum treatments on the characteristic electric properties of Si-SiON-HfO2 gate stacks. The combination of this theoretical model with experimental investigations of several differently treated HKMG devices allows the estimation of the amount of incorporated impurity atoms in different material layers. Furthermore, we propose an atomistic mechanism for the incorporation of lanthanum and fluorine impurity atoms and we can explain the results of recent leakage current measurements by a passivation of oxygen vacancies within the HfO2 layer

Nitrogen Engineering in the Ultrathin SiO2 Interface Layer of High- k CMOS Devices: A First-Principles Investigation of Fluorine, Oxygen, and Boron Defect Migration

The further development of future semiconductor devices necessitates methods for characterization on an atomic scale. This ab initio investigation reveals consequences of nitrogen treatment of the state-of-the-art high-k gate-stacks. The model allows a profound characterization of the SiO 2 interface layer for different impurity concentrations. The presented results explain recent experimental observations qualitatively as well as quantitatively. Beyond that, a fundamental understanding is given, which can be used as an essential instrument for future reliability engineering

Fluorine interface treatments within the gate stack for defect passivation in 28 nm high-k metal gate technology

A novel method of fluorine incorporation into the gate dielectric by gaseous thermal NF3 interface treatments for defect passivation have been investigated in 28nm high-k metal gate technology with respect to improvement in device reliability. The thermal treatment suppresses physical interface regrowth observed in previous plasma-assisted fluorine treatments. Detailed defect characterization by spectroscopic charge pumping is used to characterize the influence of fluorine on trap states in the interfacial oxide layer. Comprehensive structural as well as electrical characterization linked with bias temperature instability measurements indicates the potential of improving reliability in high-k metal gate technology by gaseous introduction of fluorine into the gate dielectric

Influence of nitrogen trap states on the electronic properties of high-k metal gate transistors

The origin of the defects associated with the nitridation of the interface layer between Si and HfO2 is investigated. The electronic properties change upon nitridation which impact severely the gate capacitance and gate leakage current. We modeled the temperature-dependent leakage current in SiON/HfO2 gate dielectrics for positive and negative gate voltages by means of a multi-phonon trap-assisted tunneling scheme to extract the trap distribution. The results are supported by charge pumping measurements and simulation. To clarify the origin of the additional traps in the SiON interface we performed ab-initio calculation and correlated the results with the gate leakage current measurements. Finally, we shed new light on the relation between stress-induced leakage current and positive bias temperature instability