Si-puolijohdekiteen hapettumisen hallinta ja vaikutukset

Puolijohdelaitteet ovat merkittävässä roolissa nykypäivän yhteiskunnassa. Puolijohdemateriaaleja, pääosin piitä, hyödynnetään elektroniikassa lähes kaikissa komponenteissa. Piistä valmistettavat mikroprosessorit ovat mahdollistaneet tietokoneiden ja puhelinten kehityksen. Valtaosa aurinkokennoista valmistetaan piistä. Se onkin ylivoimaisesti käytetyin puolijohdemateriaali. Piin kaikkia ominaisuuksia ei tunneta vieläkään täysin, joten sen tutkiminen on edelleen tärkeää. Uusilla löydöillä voi olla merkittäviä sovelluskohteita piin laajan hyödyntämisen vuoksi. Merkittävä kehityskohde ovat piin pinta- ja rajapintakerrokset, jotka reagoivat voimakkaasti ympäristön kanssa laitteiden valmistuksen aikana. Tässä työssä tutkittiin Si-kiteen hapettumista UHV-tyhjiöolosuhteissa, jolloin löydettiin uusi materiaali: hapettunut pii, jolla on kiderakenne. Löytö poikkeaa merkittävästi aiemmista tuloksista, koska Si-kiteen hapettuneiden pintakerrosten on aiemmin havaittu olevan amorfisia, jolla ei siis ole kiderakennetta. Tässä työssä esitetään ensimmäistä kertaa kiteinen piioksidi ja todisteet uuden materiaalin löytymiselle. Oksidin kiteisyys osoitetaan STM- ja LEED-tuloksilla, ja oksidin muodostuminen osoitetaan XPS-, STS- ja MOSCAP-tuloksilla. Tutkielmassa selvitettiin kiteisen oksidin rakennetta, sekä sen elektronisia ja sähköisiä ominaisuuksia. Näiden perusteella sille pohdittiin mahdollisia sovelluskohteita laitteissa. Lisäksi kiteisen oksidin toimintaa todellisissa laitteissa selvitettiin MOS-kondensaattorikokein. Kiteinen oksidi muodostaa Si-pintaan positiivisen varauksen, jota voidaan hyödyntää pinnan passivoimiseen. Pinnassa oleva positiivinen varaus työntää varauksenkuljettajia pois pinnasta syvemmälle kiteeseen, jolloin ne eivät pääse vuorovaikuttamaan pinnassa olevien vikatilojen kanssa. Kiteinen oksidi saattaa myös pienentää pinnan vikatilatiheyttä, mutta toistaiseksi tätä ei voida osoittaa selvästi, koska rajapinnan ominaisuuksiin vaikuttaa ainakin kaksi erilaista passivointi-ilmiötä. Pinnan passivointi muistuttaa field-effect passivation - ilmiötä, jossa pinnalla oleva ulkoinen varaus painaa varauksenkuljettajat vastaavasti pois kiteen pinnalta. Pinnan passivointi on merkittävä ongelma esimerkiksi aurinkokennoissa, joihin kiteinen oksidi voi tarjota ratkaisun. Lisäksi kiteistä oksidia voidaan hyödyntää muodostamaan hallitusti positiivinen varaus pintaan, jos se on laitteen kannalta tarpeellista. Kiteisen oksidin valmistamiseen vaadittavan UHV-tyhjiötekniikan soveltuvuutta teollisessa hyödyntämisessä on vielä selvitettävä

Evidence for the Eu 4f Character of Conduction-Band Edge at the Eu2O3 Surface Studied by Scanning Tunneling Spectroscopy

Effects of localized Eu 4f levels on the band gap properties of Eu2O3 have attracted significant fundamental and technological interest, and the band structure of such thin films has been thoroughly studied by photoelectron spectroscopies (T. Hadamek et al., J. Appl. Phys. 127 (2020) 074101). Here we apply a scanning tunneling spectroscopy (STS) to clarify the character of the conduction band (CB) bottom at the surface of epitaxial Eu2O3 grown on GaN(0001)/Si(111) substrates. It is shown that the CB edge is formed solely by an unoccupied Eu 4f state 0.8 eV above the Fermi level at the Eu2O3 surface and does not overlap with unoccupied Eu 5d6s states laying more than 2 eV higher than the bottom of the 4f band</p

Atomic and electronic structures of Si/Ge(100) interfaces studied by high-resolution photoelectron spectroscopy and scanning tunneling microscopy

The close similarity of silicon and germanium, isoelectronic group-IV elements, makes the integration of Ge layers on Si substrates suitable for technology development, but the atomic and electronic structures of Si1-xGex surfaces are still an open issue, in particular, for the alloy systems where Si is deposited on the Ge substrate. In this study, utilizing low-energy electron diffraction, scanning tunneling microscopy, and photoelectron spectroscopy using synchrotron radiation, we demonstrate that the formation mechanisms of the Si-on-Ge structures are controlled by two interface phenomena, namely Si indiffusion and Ge segregation on top of this surface. Employing these phenomena and controlling the Si quantity, one can synthesize the well-defined crystalline Ge-(2 x 1)/Si1-xGex/Ge(100) stacks where the number of Si atoms at the host Ge lattice sites can be tuned. Using the obtained data on the atomic and electronic structures of such systems, we also propose a method for interface engineering of Ge/Si/Ge stacks with tailored properties as promising templates for growing the device junctions

Stabilization of unstable and metastable InP native oxide thin films by interface effects

III-V semiconductor - oxide interfaces have attracted huge interest due to their substantial potential in electronic applications. However, due to the extreme complexity of the modeling of the interfaces, there are only few ab initio studies of these interfaces.Several model interfaces of native InPO4 oxides are designed in this study. It is shown that energies of the (quasi-)coherent interfaces are much smaller than energies of the incoherent interfaces. Furthermore, it is pointed out that the interface energy can stabilize oxide structures not found in bulk form. Relatively small strain energy and configurational match imply a small interface energy.It is estimated that the gap state density of the In-terminated quasi-coherent interfaces is small or zero. However, partial oxidation of the substrate P atoms, which can be induced, e.g., by non-stoichiometry of the oxide, causes distinct gap states. This is a mechanism to explain Fermi level pinning of the III-V - oxide interfaces. Non-stoichiometric compositions are also investigated. Experimental results on InP native oxide growth are discussed. The models can be used to study various properties of the interfaces and more complex models including, e.g., dislocations or non-planar surfaces can be based on the models.</p

Effects of thermal vacuum nitridation of Si(100) surface via NH3 exposure

Low temperature treatments to control the Si-interface properties become more and more relevant to the broad Si-based electronics and photonics technology when the back-end-of-line processing is developed and the integration of hybrid materials on the Si platform increases. In this work we have investigated effects of NH3 nitridation of three different Si surfaces in ultrahigh-vacuum (UHV) chamber at 400 °C: (i) nitridation of well-defined Si(100) (2 × 1)+(1 × 2) cleaned by the high-temperature flash heating, (ii) nitridation of the Radio Corporation of America (RCA)-cleaned H-terminated Si(100) with the final HF dip, and (iii) nitridation of the RCA-treated (without the final HF dip) Si(100) which includes so-called wet-chemical oxide of SiO2. X-ray photoelectron spectroscopy (XPS) and scanning tunneling microscopy/spectroscopy measurements show that nitrogen incorporates into subsurface layers of clean Si and into the SiO2 chemical-oxide layer, when the materials are exposed to NH3 background in UHV chamber without a plasma source at 400 °C or even at room temperature. XPS results indicate that the nitridation does not remove oxygen from the SiO2 chemical oxide. The nitridation of SiO2 is also found to increase the density of electron levels at 3 to 4 eV above the Fermi level. Electrical measurements of atomic-layer deposited HfO2/Si(100) capacitors with and without the nitridation support that the method has potential to decrease amount of interface defects and to control interface properties.​​​​​​​</ul

Atomic-Scale Modification of Oxidation Phenomena on the Ge(100) Surface by Si Alloying

Properties of Ge oxides are significantly different from those of widely used Si oxides. For example, the instability of GeOx at device junctions causes electronic defect levels that degrade the performance of Ge-containing devices (e.g., transistors and infrared detectors). Therefore, the passivating Si layers have been commonly used at Ge interfaces to reduce the effects of Ge oxide instability and mimic the successful strategy of Si oxidation. To contribute to the atomic-scale knowledge and control of oxidation of such Si-alloyed Ge interfaces (O/Si/Ge), we present a synchrotron radiation core-level study of O/Si/Ge, which is combined with scanning probe microscopy measurements. The oxidation processes and electronic properties of O/Si/Ge(100) are examined as functions of Si amount and oxidation doses. In particular, the incorporation of Si into Ge is shown to cause the strengthening of Ge−O bonds and the increase of incorporated oxygen amount in oxide/Ge junctions, supporting that the method is useful to decrease the defect-level densities.</p

Observation of Si 2p Core‐Level Shift in Si/High‐κ Dielectric Interfaces Containing a Negative Charge

Negative static charge and induced internal electric field have often been observed in the interfaces between silicon and high‐κ dielectrics, for example Al2O3 and HfO2. The electric field provides either beneficial (e.g., field‐effect passivation) or harmful (e.g., voltage instability) effect depending on the application. Different intrinsic and extrinsic defects in the dielectric film and interface have been suggested to cause the static charge but this issue is still unresolved. Here spectroscopic evidence is presented for a structural change in the interfaces where static charge is present. The observed correlation between the Si core‐level shift and static negative charge reveals the role of Si bonding environment modification in the SiO2 phase. The result is in good agreement with recent theoretical models, which relate the static charge formation to interfacial atomic transformations together with the resulting acceptor doping of SiO2

Decreasing Interface Defect Densities via Silicon Oxide Passivation at Temperatures Below 450 degrees C

Low-temperature (LT) passivation methods (700 degrees C). Therefore, the LT passivation of SiOx/Si has long been a research topic to improve application performance. Here, we demonstrate that an LT (<450 degrees C) ultrahigh-vacuum (UHV) treatment is a potential method that can be combined with current state-of-the-art processes in a scalable way, to decrease the defect densities at the SiOx/Si interfaces. The studied LT-UHV approach includes a combination of wet chemistry followed by UHV-based heating and preoxidation of silicon surfaces. The controlled oxidation during the LT-UHV treatment is found to provide an until now unreported crystalline Si oxide phase. This crystalline SiOx phase can explain the observed decrease in the defect density by half. Furthermore, the LT-UHV treatment can be applied in a complementary, post-treatment way to ready components to decrease electrical losses. The LT-UHV treatment has been found to decrease the detector leakage current by a factor of 2

Effects of post oxidation of SiO2/Si interfaces in ultrahigh vacuum below 450 °C

Growing SiO2 layer by wet-chemical oxidation of Si surfaces before growth of another insulating film(s) is a used method to passivate Si interfaces in applications (e.g., solar cell, photodiode) at low temperatures (LT) below 450 °C. We report on potential of LT ultrahigh-vacuum (UHV) treatments combined with the wet-chemical oxidation, by investigating effects of LT-UHV oxidation after the wet-chemical growth of SiO2 and before growing Al2O3 film on top of SiO2/Si. This method modifies the SiO2/Si and is found to (i) decrease defect-level density, (ii) increase negative fixed charge density, and (iii) increase carrier lifetime for Al2O3/SiO2/p-Si, as compared to state-of-the-art SiO2/p-Si reference interfaces without LT-UHV. X-ray photoelectron spectroscopy shows that the LT-UHV treatment decreases amount of Si+3 oxidized atoms in chemically grown SiO2 and also amount of carbon contamination. In order to pave the way for further tests of LT-UHV in silicon technology, we present a design of simple UHV instrument. The above-described benefits are reproduced for 4-inch silicon wafers by means of the instrument, which is further utilized to make LT-UHV treatments for complementary SiO2/Si interfaces of the native oxide at silicon diode sidewalls to decrease the reverse bias leakage current of the diodes.​​​​​​​</ul