Graphene: a perfect nanoballoon

We have performed a first-principles density functional theory investigation of the penetration of helium atoms through a graphene monolayer with defects. The relaxation of the graphene layer caused by the incoming helium atoms does not have a strong influence on the height of the energy barriers for penetration. For defective graphene layers, the penetration barriers decrease exponentially with the size of the defects but they are still sufficiently high that very large defects are needed to make the graphene sheet permeable for small atoms and molecules. This makes graphene a very promising material for the construction of nanocages and nanomembranes.Comment: 4 pages, 4 figures, submitted to Applied Physics Letter

Paramagnetic adsorbates on graphene: a charge transfer analysis

We introduce a modified version of the Hirshfeld charge analysis method and demonstrate its accurateness by calculating the charge transfer between the paramagnetic molecule NO2 and graphene. The charge transfer between paramagnetic molecules and a graphene layer as calculated with ab initio methods can crucially depend on the size of the supercell used in the calculation. This has important consequences for adsorption studies involving paramagnetic molecules such as NO2 physisorbed on graphene or on carbon nanotubes.Comment: 4 pages, 4 figures, submitted to Applied Physics Letter

On linear complementarity systems

A new method is proposed to solve dynamic linear complementary systems. To this class of systems belong all electrical piecewise linear (PL) dynamic networks. The method uses numerical integration methods to transform the original problem into a static standard linear complementary problem (LCP) that needs to be solved for each time step period. The method deals efficiently with inconsistent initial conditions and finds implicitly which mode changes and how the system equations are influenced by this chang

A wideband noise-canceling CMOS LNA exploiting a transformer

A broadband LNA incorporating single-ended to differential conversion, has been successfully implemented using a noise-canceling technique and a single on-chip transformer. The LNA achieves a high voltage gain of 19dB, a wideband input match (2.5-4.0 GHz), and a noise figure of 4-5.4 dB, while consuming only 8mW. The LNA is implemented in a 90nm CMOS process with 6 metal layers

A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from −70°C to 125°C

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim

The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS