Optimization of a Solution-Processed SiO₂ Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO₂ layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10⁻⁷ A/cm²) SiO₂ layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm²/(V s), an on/off ratio of ∼10⁷, a threshold voltage of −1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm²/(V s) and on/off ratio of ∼10⁷

Solution-Processable LaZrO_<i>x</i>/SiO₂ Gate Dielectric at Low Temperature of 180 °C for High-Performance Metal Oxide Field-Effect Transistors

Although solution-processable high-k inorganic dielectrics have been implemented as a gate insulator for high-performance, low-cost transition metal oxide field-effect transistors (FETs), the high-temperature annealing (>300 °C) required to achieve acceptable insulating properties still limits the facile realization of flexible electronics. This study reports that the addition of a 2-dimetylamino-1-propanol (DMAPO) catalyst to a perhydropolysilazane (PHPS) solution enables a significant reduction of the curing temperature for the resulting SiO₂ dielectrics to as low as 180 °C. The hydrolysis and condensation of the as-spun PHPS film under humidity conditions were enhanced greatly by the presence of DMAPO, even at extremely low curing temperatures, which allowed a smooth surface (roughness of 0.31 nm) and acceptable leakage characteristics (1.8 × 10^–6 A/cm² at an electric field of 1MV/cm) of the resulting SiO₂ dielectric films. Although the resulting indium zinc oxide (IZO) FETs exhibited an apparent high mobility of 261.6 cm²/(V s), they suffered from a low on/off current (<i>I</i>_ON/OFF) ratio and large hysteresis due to the hygroscopic property of silazane-derived SiO₂ film. The <i>I</i>_ON/OFF value and hysteresis instability of IZO FETs was improved by capping the high-k LaZrO_<i>x</i> dielectric on a solution-processed SiO₂ film via sol–gel processing at a low temperature of 180 °C while maintaining a high mobility of 24.8 cm²/(V s). This superior performance of the IZO FETs with a spin-coated LaZrO_<i>x</i>/SiO₂ bilayer gate insulator can be attributed to the efficient intercalation of the 5s orbital of In³⁺ ion in the IZO channel, the good interface matching of IZO/LaZrO_<i>x</i> and the carrier blocking ability of PHPS-derived SiO₂ dielectric film. Therefore, the solution-processable LaZrO_<i>x</i>/SiO₂ stack can be a promising candidate as a gate dielectric for low-temperature, high-performance, and low-cost flexible metal oxide FETs