A study on predictive analytics application to ship machinery maintenance

Engine failures on ships are expensive, and affect operational readiness critically due to long turn-around times for maintenance. Prior to the engine failures, there are signs of engine characteristic changes, for example, exhaust gas temperature (EGT), to indicate that the engine is acting abnormally. This is used as a precursor towards the modeling of failures. There is a threshold limit of 520 degree Celsius for the EGT prior to the need for human intervention. With this knowledge, the use of time series forecasting technique, to predict the crossing over of threshold, is appropriate to model the EGT as a function of its operating running hours and load. This allows maintenance to be scheduled just in time. When there is a departure of result from the predictive model, Cumulative Sum (CUSUM) Control charts can then be used to monitor the change early before an actual problem arises. This paper discusses and demonstrates the proof of principle for one engine and a particular operating profile of a commercial vessel with the use of predictive analytics. The realization with time series forecasting coupled with CUSUM control chart allows this approach to be extended to other attributes beyond EGT.http://archive.org/details/astudyonpredicti1094537659Civilian, Singapore Technologies Marine, Ltd.Approved for public release; distribution is unlimited

A comprehensive analysis on data hazard for RISC32 5-Stage pipeline processor

This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be used as a reference for RISC32 processor developers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set. The techniques used to resolve data hazard in this paper are data forwarding and pipeline stages stalling. When data hazard arises, it is first resolve by using data forwarding. If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard. This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling. This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises

HLA association in Singapore children with Grave's disease

Metabolism: Clinical and Experimental376518-519META

N-type behavior of ferroelectric-gate carbon nanotube network transistor

Carbon nanotube field effect transistor has attracted much attention recently and is a promising candidate for next generation nanoelectronics. Here, we report our study on a transistor using single wall carbon nanotube network as the channel and a ferroelectric film as the gate dielectric. The spontaneous polarization of ferroelectric materials offers nonvolatility and controllability of the surface charges. Modulation of >10^2 in the channel conductivity has been observed in the network-based transistor. Voltage pulses are used to control the transistor states; no continuous gate bias is needed. Furthermore, n-type behavior of the network channel is observed, which is attributed to a change in the Schottky barrier at the carbon nanotube-metal interface.Published versio

An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications

Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable micro-architecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications