The meta-stable dip (MSD) effect in SOI FinFETs

The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (V-G1), the magnitude of drain current (I-D) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (g(m)). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (V-G2), drain voltage (V-D) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates. (c) 2006 Elsevier B.V. All rights reserved

NiSi crystal structure, site preference, and partitioning behavior of palladium in NiSi(Pd)/Si(100) thin films: Experiments and calculations

The crystal structure of a NiSi thin-film on a Si substrate and Pd site-substitution in NiSi and the partitioning behavior of Pd for NiSi(Pd)/Si(100) are investigated by x-ray diffraction (XRD), first-principles calculations, and atom-probe tomography (APT). The NiSi layer is a distorted orthorhombic structure from XRD patterns via experiments and calculations. We find that Pd has a strong driving force, 0.72 eV atom À1 , for partitioning from Si into the orthorhombic NiSi layer. The calculated substitutional energies of Pd in NiSi indicate that Pd has a strong preference for Ni sublattice-sites, which is in agreement with concentration profiles determined by APT. Transition-metal silicide thin-films are extensively studied and widely used due to their low-resistivity in micro-and nano-electronic devices. 1-6 NiSi has been used for contact applications in the source, drain, and gate regions of complementary metal-oxide-semiconductor (CMOS) field-effect transistors, since 65 nm technology node. Fully silicided (FUSI) NiSi gates manufactured by a two-step self-aligned (salicide) process are also being actively studied. 8 NiSi has a lower temperature of formation, lower resistivity in narrow dimensions, and lower Si consumption, making it preferable to TiSi 2 and CoSi 2 contacts. Laser-assisted local-electrode atom-probe (LEAP) tomography utilized a pulsed laser to dissect specimens on an atom-by-atom basis at 40 K under ultrahigh vacuum conditions (<10 À10 Torr). A pulsed picosecond laser (wavelength ¼ 532 nm) operating at 250 kHz, 0.5 nJ pulse À1 , was employed to dissect a specimen with a 10 nm Ni(Pd) layer and a micro-tip length of 500 nm. LEAP tomographic samples were fabricated using a FEI Nova dual-beam focused ion-beam (FIB) microscope employing the lift-out technique. The electronic structures of pure NiSi and the sublattice site-preference of the dopant, Pd, were studied using firstprinciples calculations: full-electron (WIEN2K) (Ref. 16) and pseudo-potential calculations (VASP) (Refs. 17, 18) were utilized. Full-electron self-consistent calculations of the electronic structure and optical properties based on the scalar relativistic full-potential linearized augmented plane-wave a

Nickel Film Deposition with Varying RF Power for the Reduction of Contact Resistance in NiSi

In this study, the effect of radio frequency (RF) power on nickel (Ni) film deposition was studied to investigate the applications of lowering the contact resistance in the NiSi/Si junction. The RF powers of 100, 150, and 200 W were used for the deposition of the Ni film on an n/p silicon substrate. RMS roughnesses of 1.354, 1.174 and 1.338 nm were obtained at 100, 150, and 200 W, respectively. A circular transmission line model (CTLM) pattern was used to obtain the contact resistance for three different RF-power-deposited films. The lowest contact resistivity of 5.84 × 10−5 Ω-cm2 was obtained for the NiSi/n-Si substrate for Ni film deposited at 150 W RF power

Crystalline beryllium oxide on Si (100) deposited using E-beam evaporator and thermal oxidation

The growth characteristics and electrical properties of thin films of crystalline beryllium oxide (BeO) on Si (100) substrates grown using electron beam evaporation (EBE) are described. To expand the commercial viability of BeO, a combination of EBE with thermal oxidation was optimized to facilitate its use in nanoscale semiconductor devices. The surfaces of the EBE BeO films were found to be smooth with limited quantities of native oxides or metal silicates, as determined using atomic force measurements and X-ray photoelectron spectroscopy, respectively. Moreover, high-resolution transmission electron microscopy revealed that the films were highly crystalline. Excellent insulator properties, including a dielectric constant of 6.77 and a breakdown voltage of 8.3 MV/cm, were deduced from a series of capacitance???voltage and leakage current measurements. Reflection electron energy loss spectroscopy and ultraviolet photoelectron spectroscopy indicated that the films exhibited a high band gap of 8.6 eV and a high conduction band offset of 3.43 eV. Collectively, these results indicate that EBE BeO films hold promise for use as electrical insulators in Si CMOS and nanoscale device applications

Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N2 plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N2 plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed

Lymphatic vessel mapping in the upper extremities of a healthy Korean population

Background Intraoperative indocyanine green (ICG) lymphography can effectively detect functioning lymph vessels in edematous limbs. However, it is sometimes difficult to clearly identify their course in later-stage edematous limbs. For this reason, many surgeons rely on experience when they decide where to make the skin incision to locate the lymphatic vessels. The purpose of this study was to elucidate lymphatic vessel flow patterns in healthy upper extremities in a Korean population and to use these findings as a reference for lymphedema treatment. Methods ICG fluorescence lymphography was performed by injecting 1 mL of ICG into the second web space of the hand. After 4 hours, fluorescence images of lymphatic vessels were obtained with a near-infrared camera, and the lymphatic vessels were marked. Three landmarks were designated: the radial styloid process, the mid-portion of the cubital fossa, and the lower border of the deltopectoral groove. A straight line connecting the points was drawn, and the distance between the connected lines and the marked lymphatic vessels was measured at 8 points. Results There were 30 healthy upper extremities (15 right and 15 left). The average course of the main lymph vessels passed 26.0±11.6 mm dorsal to the styloid process, 5.7±40.7 mm medial to the mid-cubital fossa, and 31.3±26.1 mm medial to the three-quarters point of the upper landmark line. Conclusions The main functioning lymphatic vessel follows the course of the cephalic vein at the forearm level, crosses the mid-cubital point, and travels medially toward the mid-axilla

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability