Power and area efficient MOSFET-C filter for very low frequency applications

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of \hbox{M}\Upomega to few hundreds of \hbox{G}\Upomega , the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency (f C =20Hz-184kHz) has been implemented in a conventional 0.18μm CMOS technology. Occupying 0.045mm2/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 d

MoS2 Transistors Operating at Gigahertz Frequencies

The presence of a direct band gap and an ultrathin form factor has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulphide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, logic circuits and optoelectronic devices have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on two-dimensional semiconductors.Comment: Nano Letters (2014), Supplementary information available at http://dx.doi.org/10.1021/nl502863

Modeling Electrical Resistance Drift with Ultrafast Saturation of OTS Selectors

Crossbar array architecture is an essential design element for densely connected Non-Volatile Memory(NVM) applications. To overcome intrinsic sneak current problem of crossbar arrays, each memory unit is serially attached to a selector unit with highly nonlinear current-voltage (I-V) characteristics. Recently, Ovonic Threshold Switching (OTS) materials are preferred as selectors due to their fabrication compatibility with PRAM, MRAM or ReRAM technologies; however, OTS selectors suffer from the temporal drift of its threshold voltage. First, based on Poole-Frenkel conduction, we present time and temperature dependent model that predicts temporally evolving I-V characteristics,including threshold voltage of OTS selectors. Second, we report an ultrafast saturation ($\sim 10^3$ seconds) of the drift and extend the model to predict the time of drift saturation. Our model shows excellent agreement with OTS devices fabricated with 8 nm technology node at 25{\deg}C and 85{\deg}C ambient temperatures. The proposed model plays a significant role in understanding OTS device internals and the development of reliable threshold voltage jump table

Modeling Electrical Resistance Drift with Ultrafast Saturation of OTS Selectors

Crossbar array architecture is an essential design element for densely connected Non-Volatile Memory(NVM) applications. To overcome intrinsic sneak current problem of crossbar arrays, each memory unit is serially attached to a selector unit with highly nonlinear current-voltage (I-V) characteristics. Recently, Ovonic Threshold Switching (OTS) materials are preferred as selectors due to their fabrication compatibility with PRAM, MRAM or ReRAM technologies; however, OTS selectors suffer from the temporal drift of its threshold voltage. First, based on Poole-Frenkel conduction, we present time and temperature dependent model that predicts temporally evolving I-V characteristics,including threshold voltage of OTS selectors. Second, we report an ultrafast saturation (∼103 seconds) of the drift and extend the model to predict the time of drift saturation. Our model shows excellent agreement with OTS devices fabricated with 8 nm technology node at 25°C and 85°C ambient temperatures. The proposed model plays a significant role in understanding OTS device internals and the development of reliable threshold voltage jump table

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm² × fJ/conv-step Efficiency and 0.97 NEF

This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy–area efficiency compared to the state of the art with 164 μm×40μm footprint and 0.78 mm²× fJ/conv-step energy-area figure of merit. The measured 0.65- μW power consumption and 3.1 - μVrms input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm² × fJ/conv-step Efficiency and 0.97 NEF

This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy–area efficiency compared to the state of the art with 164 μm×40μm footprint and 0.78 mm²× fJ/conv-step energy-area figure of merit. The measured 0.65- μW power consumption and 3.1 - μVrms input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted simply through a controlling bias current. The filter has low-pass characteristics with $f_{c}$ = 20Hz to 184kHz while exhibiting a constant power consumption per cutoff frequency over its entire tuning range that is almost four decades wide. The proposed MOSFET-C filter uses PMOS transistors in subthreshold regime for implementing floating and widely adjustable resistors. The ultra high resistivity of the PMOS devices makes them very suitable for implementing very low frequency and compact filters. Realized in 0.18$\mu$m CMOS technology, the filter exhibits a relatively constant noise and linearity performance over its entire tuning range. The active area of the proposed MOSFET-C filter is 0.09mm$^2$

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations and hotspot locations are studied. The influence of local power density on peak temperature is examined. It is shown that high power density devices have significant influence on peak temperature in FDSOI. It is found that some group of devices that perform the same function are the most prominent heat generators. A modification on the design of these devices is proposed which decreases the hotspot temperatures significantly