3 research outputs found

    Building a Blockchain-based API Access Control System

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    API providers can expose their service and data via APIs. However, there must be an access control mechanism in place to control which client can access the APIs. Blockchain technology holds significant potential for this use case. While blockchain may introduce latency, it also offers inherent features including decentralization, data immutability, scalability, and traceability. This thesis explores implementing a blockchain-based access control system and conducts performance evaluations. The proposed comprehensive solution features a straightforward architecture and a user-friendly web interface. It has been deployed in a cloud environment for development, testing, and performance assessments. Extensive experiments have been conducted to analyze latency and determine the system's breaking point. It can withstand 14000 client apps loading it simultaneously within the cloud environment where it was deployed

    Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

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    This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it

    Nonlinear Stability Analysis of Eccentrically Stiffened Functionally Graded Truncated Conical Sandwich Shells with Porosity

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    This paper analyzes the nonlinear buckling and post-buckling characteristics of the porous eccentrically stiffened functionally graded sandwich truncated conical shells resting on the Pasternak elastic foundation subjected to axial compressive loads. The core layer is made of a porous material (metal foam) characterized by a porosity coefficient which influences the physical properties of the shells in the form of a harmonic function in the shell’s thickness direction. The physical properties of the functionally graded (FG) coatings and stiffeners depend on the volume fractions of the constituents which play the role of the exponent in the exponential function of the thickness direction coordinate axis. The classical shell theory and the smeared stiffeners technique are applied to derive the governing equations taking the von Kármán geometrical nonlinearity into account. Based on the displacement approach, the explicit expressions of the critical buckling load and the post-buckling load-deflection curves for the sandwich truncated conical shells with simply supported edge conditions are obtained by applying the Galerkin method. The effects of material properties, core layer thickness, number of stiffeners, dimensional parameters, semi vertex angle and elastic foundation on buckling and post-buckling behaviors of the shell are investigated. The obtained results are validated by comparing with those in the literature
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