PERFORMANCE ANALYSIS OF FINFET BASED INVERTER, NAND AND NOR CIRCUITS AT 10 NM ,7 NM AND 5 NM NODE TECHNOLOGIES

Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore’s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements.This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current ION, the leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET with different nodes are presented in this simulation.The aim and the novelty  of this paper is to extract the operating frequency for CMOS circuits using Quantum and Stress effects implemented in the Spice parameters on the latest Microwind software. The simulation results show a fitting with experimental data  for FinFET N and P 10 nm strctures using quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach a minimum time delay of  td=1.4 ps for CMOS NOT gate and td=1 ps  for CMOS NOR gate to improve Integrated Circuits IC

PERFORMANCE ANALYSIS AND OPTIMIZATION OF 10 NM TG N- AND P-CHANNEL SOI FINFETS FOR CIRCUIT APPLICATIONS

This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P-channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD with the Bohm quantum potential (BQP) algorithm. The influence of the geometrical parameters on the threshold voltage VTH, the subthreshold swing (SS), the transconductance and the on/off current ratio, ION/IOFF, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P-FinFET can reach a minimum SS value with Fin heights of 15 nm and 9 nm, respectively. In addition, low threshold voltages of 0.61 V and 0.27 V for N- and P-channel SOI FinFETs, respectively, are obtained at a Fin width of 7 nm