IMPLEMENTATION OF LOW POWER AND DELAY SCALABLE CHANNEL PARALLEL NAND FLASH MEMORY CONTROLLER ARCHITECTURE USING ALU

RISC refers to Reduced Instruction Set Computer. Which means the computer that consists of RISC processor contains reduced (simple) instructions for performing necessary and required operations. Any chip if considered as processor, it should have the capability of performing certain operations like arithmetic, logical, control and data transfer. For performing these operations, a processor should contain some major blocks as Control unit (CU), Flexible computational unit (FCU), Program counter (PC), Accumulator, Instruction register, Memory and additional logic. RISC actually enhances the performance of processor by considering the factors like simple architecture construction and instruction set, easy instruction set for decoding and simplified control architecture. This paper proposes a simple 32 bit RISC processor by using Peres reversible logic gates, which is expected to reduce the size then the conventional architecture that is based on carry save logic adder approach. The synthesis and simulation is carried out using XILINX ISE 12.3i and HDL is developed using VERILOG language