The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes

Electrical characterisation of highly doped triangular silicon nanowires

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using Silicon-on Insulator (SOI) as the starting substrate. Initially, the samples were doped with phosphorus using the diffusion process resulting in carrier concentration of 2 X 10 18 cm-3. After the silicon nanowires were fabricated, they were measured using a dual configuration method which is similar to the four-point probe measurement technique to deduce its resistivity. The data obtained had suggested that the doping distribution in the silicon nanowires were lower and this may have been affected by the surface depletion effect. In addition, with respect to carrier mobility, the effective mobility of electrons extracted using the four-point probe data had demonstrated that the mobility of carriers in the silicon nanowire is comparable with the bulk mobility. This is most probably due to the fact that in this research, the quantum confinement effect on these nanowires is not significant

Material characterization of a doped triangular silicon nanowire using raman spectroscopy

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using a doped Silicon-on Insulator (SOI) as the starting substrate. The use of ODE etchant such as potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) is known to create geometrical structures due to its anisotropic mechanism of etching. The SOI is doped with an n-type dopant (phosphorus) and the doped silicon nanowire is then characterized using Raman Spectroscopy. Due to the changes in the silicon structure, the result shows that the highly doped silicon nanowire has a wider Full Width Half Maximum (FWHM) as compared to the undoped silicon substrate

Improved analog performance in strained-Si MOSFETs using the thickness of the silicon-germanium strain-relaxed buffer as a design parameter

The impact of self-heating in strained-Si MOSFETs on the switching characteristics of a complementary-metal-oxide-semiconductor (CMOS) inverter and the voltage gain of a push-pull inverting amplifier is assessed by technology-computer-aided-design (TCAD) simulations. Strained-Si nMOSFETs on 4-mum- and 425-nm-thick silicon-germanium strain-relaxed buffers (SiGe SRB) are cofabricated with silicon control nMOSFETs and used to calibrate the TCAD models. The measured data show a 50% reduction in thermal resistance from 30.5 to 16.6 K middot mW-1 as the thickness of the SiGe SRB is scaled from 4 mum to 425 nm. Using the calibrated models, electrothermal simulations of CMOS inverters are performed by accounting for heat generation from carrier flow using the fully coupled energy-balance equations for electrons and holes. The results of the TCAD simulations show that the inverter voltage gain can be maximized by balancing the opposing effects of drain induced barrier lowering (DIBL) and self-heating i.e. DIBL increases the drain conductance whereas self-heating reduces the drain conductance. DIBL is shown to limit the simulated voltage gain of the Si control inverter, whereas self-heating in the strained-Si nMOSFET on the 4-mum-thick SiGe SRB is shown to cause anomalous operation in the simulated inverter characteristics. The inverter voltage transfer characteristics simulated with the strained-Si nMOSFETs on the 425-nm SiGe SRB exhibited the highest voltage gain. The thickness of the SiGe SRB is presented as a design parameter for optimizing the analog performance of strained-Si MOSFETs

The study on the aspect ratio of Atomic Force Microscope (AFM) measurements for Triangular Silicon Nanowire

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching (ODE) has been developed using Silicon-on Insulator (SOI) as the starting substrate. The use of ODE etchant such as potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) is known to create geometrical structures due to its anisotropic mechanism of etching. In this process flow, using the SOI substrate, a triangular shape silicon nanowire is successfully fabricated. The triangle silicon nanowire has planes on each side which theoretically produces an angle of 54.7 with the horizontal plane. One of the geometrical characterizing methods that were used to confirm the fabrication of the silicon nanowire is by using Atomic Force Microscope (AFM). In this paper, the study on the aspect ratio of the AFM measurements is presented. This experimental study would demonstrate the importance of having a high aspect ratio cantilever when a nanowire with a thickness of less than 200 nm is concerne

Optimization of the process modules for a top-down silicon nanowire fabrication using optical lithography and orientation dependent etching

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching has been developed using Silicon-on Insulator (SOI) as the starting substrate. The design of experiments for the optimization of the process flow especially on the orientation dependent etching using potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) are presented in this paper. Based on the etching experiments using silicon substrates, KOH with added isopropyl alcohol (IPA) had shown to have a consistent etch rate with acceptable silicon surface roughness as compared with its other counterparts. The concern regarding the effect of line edge roughness (LER) as a result of optical lithography was highlighted and, therefore, the optimization of the patterning procedure was also discussed and presented

Top-down fabrication of single crystal silicon nanowire using optical lithography

A method for fabricating single crystal silicon nanowires is presented using top-down optical lithography and anisotropic etching. Wire diameters as small as 10 nm are demonstrated using silicon on insulator substrates. Structural characterization confirms that wires are straight, have a triangular cross section and are without breakages over lengths of tens of microns. Electrical characterization indicates bulk like mobility values, not strongly influenced by surface scattering or quantum confinement. Processing is compatible with conventional silicon technology having much larger critical dimensions. Integrating such nanowires with a mature CMOS technology offers an inexpensive route to their exploitation as sensors

Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers

Strained Si/SiGe devices offer a route to high speed digital devices. Analog design trade-offs can also be improved using strained Si if device self-heating can be controlled; strained Si is generated using a strain relaxed buffer (SRB) of SiGe which has a lower thermal conductivity compared with bulk Si. In this work the impact of the SiGe SRB thickness on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self heating at high power levels leads to negative self gain and anomalous circuit behavior in terms of nonlinear phase shifts. By using ac and dc measurements we show that by reducing the SRB thickness self-heating effects are significantly lower and the analog design space is improved. The range of gate voltages that leverage positive self gain in 100 nm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by 100% compared with strained Si devices fabricated on conventional SRBs 4 mum thick. Guidelines for the maximum SRB thicknesses required to obtain positive self gain for highly scaled technology generations where self-heating effects increase are presented. For a 22 nm technology node, the SRB thickness should not exceed 20 nm for 1.5 V drain voltage and gate overdrive. The thin SRB is grown using a C-layer and does not compromise any aspect of device performance