Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.Comment: 18 pages, 11 figure

Planar Electrostatically Doped Reconfigurable Schottky Barrier FDSOI Field-Effect Transistor Structures

In the last 50 years, our economy and society have obviously been influenced and shaped to a great extent by electronic devices. This substantial impact of electronics is the result of a continuous performance improvement based on the scaling, i.e. shrinking, of MOSFET devices in complementary integrated circuits, following Moore's law. As the MOSFET feature sizes are approaching atomistic dimensions, the scaling trend slowed down considerably and is even threatened for sub-10 nm technology nodes. Further, additional advancements are increasingly difficult to realize both from the technological and especially the economical perspective. Therefore, technologies that have the potential to supersede the CMOS technology in the future are the topic of intensive investigation by both researchers and the industry. An attractive solution is the leveraging of existing semiconductor technologies based on emerging research devices (ERD) offering novel characteristics, which enable new circuit architectures in future nanoscale logic circuits. A possible ERD contender are polarity controllable or reconfigurable MOSFET (RFET) concepts. Generally, RFET devices are able to switch between n- and p-type conduction by the application of an electrical signal. Therefore, RFET promise increased complex systems with a lower device count decreasing the costs per basic logic function based on their higher logic expressiveness. The focus of this work lies in the successful transfer of a predecessor silicon nanowire (NW) RFET technology into a planar RFET device, while simultaneously optimizing the resulting RFET for reconfigurable as well as conventional CMOS circuits. As for the predecessor NW RFET, the planar approach features a doping-less CMOS compatible fabrication process on a conventional SOI substrate and obtains its reconfigurability by electrostatic doping. The device can be regarded as a entanglement of two MOSFET in one structure, i.e. a depletion mode FET centered on top of a backside enhancement mode Schottky barrier FET (SBFET). The backside SBFET establishes the conductive channel consisting of the desired charge carrier type via an appropriate potential on its gate electrode. The topside FET controls the charge carrier flow between source and drain by locally depleting this channel given an opposite potential on its gate electrode with respect to the backside gate electrode. Two generations of devices have been successfully processed, while different gate electrode materials, i.e. nickel, aluminum and reactively sputtered tungsten-titanium-nitride, have been introduced to the device structure. As n- and p-type symmetry of the very same device is essential for RFET circuit design, tungsten-titanium-nitride is experimentally identified as a possible mid-gap metal gate electrode for RFET devices. Also, a Schottky barrier adjustment process for ideal n- and p-type symmetry based on silicide induced dopant segregation is experimentally demonstrated. Extensive electrical characterizations supported by calibrated TCAD simulations are presented, demonstrating experimental sub-threshold slopes of 65 mV/dec and on-to-off current ratios of over 9 decades. Based on TCAD simulations and supported by experimental results, the design space of the device concept is explored in order to gather predictive results for future scaled device optimization. Further, the high temperature (HT) performance is evaluated and compared to the predecessor NW RFET devices as well as to a state-of-the-art industrial high reliability HT MOSFET clearly illustrating the on par performance of the planar RFET concept with respect to off-state leakage current

Belief, Credence and Statistical Evidence

According to the Rational Threshold View, a rational agent believes p if and only if her credence in p is equal to or greater than a certain threshold. One of the most serious challenges for this view is the problem of statistical evidence: statistical evidence is often not sufficient to make an outright belief rational, no matter how probable the target proposition is given such evidence. This indicates that rational belief is not as sensitive to statistical evidence as rational credence. The aim of this paper is twofold. First, we argue that, in addition to playing a decisive role in rationalizing outright belief, non-statistical evidence also plays a preponderant role in rationalizing credence. More precisely, when both types of evidence are present in a context, non-statistical evidence should receive a heavier weight than statistical evidence in determining rational credence. Second, based on this result, we argue that a modified version of the Rational Threshold View can avoid the problem of statistical evidence. We conclude by suggesting a possible explanation of the varying sensitivity to different types of evidence for belief and credence based on the respective aims of these attitudes

Field Effect Transistor Arrangement

The invention relates to a field effect transistor arrangement having a planar channel layer (1) consisting of semiconductor material, the whole surface of the underside of said layer being applied to an upper side of an electrically insulating substrate layer (2) and the upper side of said planar channel layer being covered by an insulation layer (3). The arrangement has a source electrode (6) on a first side edge of the channel layer (1) and a drain electrode (7) on a second side edge of the channel layer (1) and a control electrode (9) arranged above the channel layer (1). An adjusting electrode (5) is arranged on an underside of the substrate layer (2). A contact region (8) between the source and drain electrodes (6) and the planar channel layer (1) is in each case configured as a midgap Schottky barrier. A respective barrier control electrode (10) is arranged in the vicinity of the contact region (8) of the source electrode (6) and of the drain electrode (6). Each barrier control electrode (10) can have a section (11) that projects outwards in the direction of the planar channel layer (1)

Feldeffekttransistor-Anordnung

Eine Feldeffekttransistor-Anordnung mit einer planaren Kanalschicht (1) aus einem Halbleitermaterial, die mit einer Unterseite flächig auf einer Oberseite einer elektrisch isolierenden Untergrundschicht (2) aufgebracht ist und auf einer Oberseite von einer elektrisch isolierenden Elektrodenisolierungsschicht (3) bedeckt ist, weist eine Source-Elektrode (6) an einer ersten Seitenkante der Kanalschicht (1) und eine Drain-Elektrode (7) an einer zweiten Seitenkante der Kanalschicht (1) sowie eine über der Kanalschicht (1) zwischen der Source-Elektrode (6) und der Drain-Elektrode (7) angeordnete Steuerelektrode (9) auf. An einer Unterseite der Untergrundschicht (2) ist eine Einstellelektrode (5) angeordnet. Ein Kontaktbereich (8) zwischen der Source-Elektrode (6) und der planaren Kanalschicht (1) sowie ein Kontaktbereich (8) zwischen der Drain-Elektrode (7) und der planaren Kanalschicht (1) ist jeweils als eine Midgap-Schottky-Barriere ausgestaltet. In der Nähe des Kontaktbereichs (8) der Source-Elektrode (6) und in der Nähe des Kontaktbereichs (8) der Drain-Elektrode (6) ist jeweils eine Barrieresteuerelektrode (10) angeordnet. Die Barrieresteuerelektroden (10) können jeweils eine in Richtung der planaren Kanalschicht (1) vorspringende Ausformung (11) aufweisen. Die Steuerelektrode (9) kann zwei verschiedene Metalle mit unterschiedlichen Austrittsarbeiten aufweisen. Die Einstellelektrode (5) kann eine Dotierung aufweisen