Light-induced charge transfer in pyrene/CdSe-SWNT hybrids

On account of their nano-scale size, large aspect ratio and high conductivity, single-walled carbon nanotubes(SWNTs) have emerged as an attractive choice for conducting composite materials. [1–10] Composites in corporating SWNTs show percolation dominated conductivity with a much lower volume threshold (volumefraction≈10–5), compared to those with nanoparticles.[11–13] Two-thirds of SWNTs a rep-typesemicon-ductors with holes as the charge carriers.Using the hole-blocking nature of SWNTs, conducting polymer shaving SWNTs as dopants are effectively used as the hole buffering [14] and electron transport[15] layers in organic light-emitted diodes(OLEDs). For the active layer of OLEDs and organic photovoltaic(OPV) devices, incorporation of SWNTs enhances the charge separation and facilitates charge transport, hence improving the performance, i.e., the short circuit current, the filling fact or and power conversion efficiency.[16–19] However, since SWNTs are a mixture of metallic and semi-conducting nano tubes with a small bandgap(≈0.6eV), both electrons and holes in the composite matrix prefer[14] to transfer on to and then be quenched on the SWNTs.Accepted versio

CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO2 wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 μm, with high current density 20 μA/μm and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain ~5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits

Raman Characterization and Polarity Tuning of Aligned Single-Walled Carbon Nanotubes on Quartz

Raman characterization has been employed to study key features of highly aligned single-walled carbon nanotubes grown on quartz substrates. The nanotubes are observed to possess an estimated metallic/semiconducting ratio of 1:2.7, and Raman spectra also confirm the high integrity of nanotubes before and after being transferred from quartz to Si/SiO2 substrates. Based on the as-grown and the transferred aligned nanotubes, we have further fabricated top- and back-gated nanotube devices, respectively. The top-gated transistors exhibit ambipolar transport characteristics with high transconductance, small subthreshold swing of 110 mV/decade and on/off ratio of 107, while the back-gated transistors show unipolar p-type characteristics. Furthermore, we have demonstrated polarity tuning to produce both predominately n- and p-type top-gated carbon nanotube transistors by controlling the polarity of gate voltage during electrical breakdown, which has great potential for building complementary carbon nanotube circuits.Chemistry and Chemical Biolog

Carbon Nanotube Memory by the Self-Assembly of Silicon Nanocrystals as Charge Storage Nodes

A memory structure based on self-aligned silicon nanocrystals (Si NCs) grown over Al₂O₃-covered parallel-aligned carbon nanotubes (CNTs) by gas source molecular beam epitaxy is reported. Electrostatic force microscopy characterizations directly prove the charging and discharging of discrete NCs through the Al₂O₃ layer covering the CNTs. A CNT field effect transistor based on the NC/CNT structure is fabricated and characterized, demonstrating evident memory characteristics. Direct tunneling and Fowler–Nordheim tunneling phenomena are observed at different programming/erasing voltages. Retention is demonstrated to be on the order of 10⁴ s. Although there is still plenty of room to enhance the performance, the results suggest that CNT-based NC memory with diminutive CNTs and NCs could be an alternative structure to replace traditional floating gate memory

Comparison of Graphene Growth on Single-Crystalline and Polycrystalline Ni by Chemical Vapor Deposition

We report a comparative study and Raman characterization of the formation of graphene on single crystal Ni (111) and polycrystalline Ni substrates using chemical vapor deposition (CVD). Preferential formation of monolayer/bilayer graphene on the single crystal surface is attributed to its atomically smooth surface and the absence of grain boundaries. In contrast, CVD graphene formed on polycrystalline Ni leads to a higher percentage of multilayer graphene (≥3 layers), which is attributed to the presence of grain boundaries in Ni that can serve as nucleation sites for multilayer growth. Micro-Raman surface mapping reveals that the area percentages of monolayer/bilayer graphene are 91.4% for the Ni (111) substrate and 72.8% for the polycrystalline Ni substrate under comparable CVD conditions. The use of single crystal substrates for graphene growth may open ways for uniform high-quality graphene over large areas