III-Nitride Transistors with Capacitively Coupled Contacts

AlGaN∕GaNheterostructure field-effect transistor design using capacitively coupled contacts (C3HFET) is presented. Insulated-gate [C3 metal-oxide-semiconductor HFET(C3MOSHFET)] has also been realized. The capacitively coupled source, gate, and drain of C3 device do not require annealedOhmic contacts and can be fabricated using gate alignment-free technology. For typical AlGaN∕GaNheterostructures, the equivalent contact resistance of C3 transistors is below 0.6Ωmm. In rf-control applications, the C3HFET and especially the C3MOSHFET have much higher operating rf powers as compared to HFETs.C3 design is instrumental for studying the two-dimensional electron gas transport in other wide band gap heterostructures such as AlN∕GaN, diamond, etc., where Ohmic contact fabrication is difficult

Digital Oxide Deposition of SiO\u3csub\u3e2\u3c/sub\u3e Layers for III-Nitride Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors

We present a digital-oxide-deposition (DOD) technique to deposit high quality SiO2dielectric layers by plasma-enhanced chemical vapor deposition using alternate pulses of silicon and oxygen precursors. The DOD procedure allows for a precise thickness control and results in extremely smooth insulating SiO2 layers. An insulating gate AlGaN∕GaNheterostructurefield-effect transistor(HFET) with 8nm thick DOD SiO2dielectric layer had a threshold voltage of −6V (only 1V higher than that of regular HFET), very low threshold voltage dispersion, and output continuous wave rf power of 15W∕mm at 55V drain bias

Si\u3csub\u3e3\u3c/sub\u3eN\u3csub\u3e4\u3c/sub\u3e/AlGaN/GaN-Metal-Insulator-Semiconductor Heterostructure Field-Effect Transistors

We report on a metal–insulator–semiconductor heterostructurefield-effect transistor (MISHFET) using Si3N4 film simultaneously for channel passivation and as a gate insulator. This design results in increased radio-frequency (rf) powers by reduction of the current collapse and it reduces the gate leakage currents by four orders of magnitude. A MISHFET room temperature gate current of about 90 pA/mm increases to only 1000 pA/mm at ambient temperature as high as 300 °C. Pulsed measurements show that unlike metal–oxide–semiconductor HFETs and regular HFETs, in a Si3N4 MISHFET, the gate voltage amplitude required for current collapse is much higher than the threshold voltage. Therefore, it exhibits significantly reduced rf current collapse

Maximum Current in Nitride-Based Heterostructure Field-Effect Transistors

We present experimental and modeling results on the gate-length dependence of the maximum current that can be achieved in GaN-based heterostructurefield-effect transistors(HFETs) and metal–oxide–semiconductor HFETs (MOSHFETs). Our results show that the factor limiting the maximum current in the HFETs is the forward gate leakage current. In the MOSHFETs, the gate leakage current is suppressed and the overflow of the two dimensional electron gas into the AlGaN barrier region becomes the most important factor limiting the maximum current. Therefore, the maximum current is substantially higher in MOSHFETs than in HFETs. The measured maximum current increases with a decrease in the gate length, in qualitative agreement with the model that accounts for the velocity saturation in the channel and for the effect of the source series resistance. The maximum current as high as 2.6 A/mm can be achieved in MOSHFETs with a submicron gate

Thermal Management of AlGaN-GaN HFETs on Sapphire Using Flip-Chip Bonding with Epoxy Underfill

Self-heating imposes the major limitation on the output power of GaN-based HFETs on sapphire or SiC. SiC substrates allow for a simple device thermal management scheme; however, they are about a factor 20-100 higher in cost than sapphire. Sapphire substrates of diameters exceeding 4 in are easily available but the heat removal through the substrate is inefficient due to its low thermal conductivity. The authors demonstrate that the thermal impedance of GaN based HFETs over sapphire substrates can be significantly reduced by implementing flip-chip bonding with thermal conductive epoxy,underfill. They also show that in sapphire-based flip-chip mounted devices the heat spread from the active region under the gate along the GaN buffer and the substrate is the key contributor to the overall thermal impedance

Induced Strain Mechanism of Current Collapse in AlGaN/GaN Heterostructure Field-Effect Transistors

Gated transmission line model pattern measurements of the transient current–voltage characteristics of AlGaN/GaN heterostructurefield-effect transistors(HFETs) and metal–oxide–semiconductor HFETs were made to develop a phenomenological model for current collapse. Our measurements show that, under pulsed gate bias, the current collapse results from increased source–gate and gate–drain resistances but not from the channel resistance under the gate. We propose a model linking this increase in series resistances (and, therefore, the current collapse) to a decrease in piezoelectriccharge resulting from the gate bias-induced nonuniform strain in the AlGaN barrier layer

Mechanism of Radio-Frequency Current Collapse in GaN-AlGaN Field-Effect Transistors

The mechanism of radio-frequency current collapse in GaN–AlGaN heterojunctionfield-effect transistors(HFETs) was investigated using a comparative study of HFET and metal–oxide–semiconductor HFET current–voltage (I–V) and transfer characteristics under dc and short-pulsed voltage biasing. Significant current collapse occurs when the gate voltage is pulsed, whereas under drain pulsing the I–V curves are close to those in steady-state conditions. Contrary to previous reports, we conclude that the transverse electric field across the wide-band-gap barrier layer separating the gate and the channel rather than the gate or surface leakage currents or high-field effects in the gate–drain spacing is responsible for the current collapse. We find that the microwave power degradation in GaN–AlGaN HFETs can be explained by the difference between dc and pulsed I–Vcharacteristics

Real-Space Electron Transfer in III-Nitride Metal-Oxide-Semiconductor-Heterojunction Structures

The real-space transfer effect in a SiO2∕AlGaN∕GaN metal-oxide-semiconductor heterostructure (MOSH) from the two-dimensional (2D) electron gas at the heterointerface to the oxide-semiconductor interface has been demonstrated and explained. The effect occurs at high positive gate bias and manifests itself as an additional step in the capacitance-voltage (C‐V) characteristic. The real-space transfer effect limits the achievable maximum 2D electron gas density in the device channel. We show that in MOSH structures the maximum electron gas density exceeds up to two times that at the equilibrium (zero bias) condition. Correspondingly, a significant increase in the maximum channel current (up to two times compared to conventional Schottky-gate structures) can be achieved. The real-space charge transfer effect in MOSH structures also opens up a way to design novel devices such as variable capacitors, multistate switches, memory cells, etc

AlGaN/GaN/AlGaN Double Heterostructure for High-Power III-N Field-Effect Transistors

We propose and demonstrate an AlGaN/GaN/AlGaN double heterostructure (DH) with significantly improved two-dimensional (2D) confinement for high-power III-N heterostructurefield-effect transistors(HFETs). The DH was grown directly on an AlN buffer over i-SiC substrate. It enables an excellent confinement of the 2D gas and also does not suffer from the parasitic channel formation as experienced in past designs grown over GaN buffer layers. Elimination of the GaN buffer modifies the strain distribution in the DH, enabling Al contents in the barrier region well over 30%. For the AlGaN/GaN/AlGaN DH design, the 2D electron gasmobility achieved was 1150 cm2/V s at room temperature and 3400 cm2/V s at 77 K, whereas the temperature independent sheet carrier density was NS≈1.1×1013 cm−2. Compared to a regular AlGaN/GaN structure, the channel mobility-concentration profiling shows significant improvement in the carrier confinement. Sample DHFETs with 1-μm long gates demonstrate the threshold voltage of 3.5 V, with a peak saturation current of 0.6–0.8 A/mm