FSMD-Based Hardware Accelerators for FPGAs

Current VLSI technology allows the design of sophisticated digital systems with escalated demands in performance and power/energy consumption. The annual increase of chip complexity is 58%, while human designers productivity increase is limited to 21 % per annum (ITRS, 2011). The growing technology-productivity gap is probably the most importan

System-level modeling of dynamically reconfigurable hardware with SystemC

To cope with the increasing demand for higher computational power and flexibility, dynamically re-configurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the re-configurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation. 1

Effect of Data Transfer and Storage Optimization on Design Quality Factors of Multimedia Algorithms Realized on Instruction Set Processors

Abstract. A systematic methodology for data transfer and storage optimization of multimedia algorithms realized on programmable platforms has been developed. The methodology reduces both the sizes of and the number of accesses to the array type data structures of the target algorithm. This leads to power consumption and performance improvement. In this paper the effect of data transfers and storage optimization on different design quality factors of multimedia applications realized on instruction set processors is explored. Emphasis is given on the way processor’s performance with respect to arithmetic operations and external bus load are affected.