12 research outputs found

    Comparing the performance of Organic-inorganic hybrid tandem multijunction solar cells of different organic bulk thicknesses

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    In this study, J-V curves of a-Si:H/PCPDTBT:PC70BM hybrid tandem solar cells were simulated using a modified drift-diffusion model, and the influence of the thickness of the organic blend layer was investigated. The results of the simulations were compared with experimental data from literature.It is shown that as the thickness of the blend layer increases, the fill factor and the voltage corresponding to maximum power point decrease whereas the maximum power point and the short circuit current density of solar cell increase up to thicknesses of 60 nm and 138 nm respectively. Finally, the modified organic solar cell was used as second sub-cell and the power conversion efficiency increased from 1.90% to 2.1% in simulation

    Effect of p-Layer and i-Layer Properties on the Electrical Behaviour of Advanced a-Si:H/a-SiGe:H Thin Film Solar Cell from Numerical Modeling Prospect

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    The effect of p-layer and i-layer characteristics such as thickness and doping concentration on the electrical behaviors of the a-Si:H/a-SiGe:H thin film heterostructure solar cells such as electric field, photogeneration rate, and recombination rate through the cell is investigated. Introducing Ge atoms to the Si lattice in Si-based solar cells is an effective approach in improving their characteristics. In particular, current density of the cell can be enhanced without deteriorating its open-circuit voltage. Optimization shows that for an appropriate Ge concentration, the efficiency of a-Si:H/a-SiGe solar cell is improved by about 6% compared with the traditional a-Si:H solar cell. This work presents a novel numerical evaluation and optimization of amorphous silicon double-junction (a-Si:H/a-SiGe:H) thin film solar cells and focuses on optimization of a-SiGe:H midgap single-junction solar cell based on the optimization of the doping concentration of the p-layer, thicknesses of the p-layer and i-layer, and Ge content in the film. Maximum efficiency of 23.5%, with short-circuit current density of 267 A/m2 and open-circuit voltage of 1.13 V for double-junction solar cell has been achieved

    Osdes_net: oil spill detection based on efficient_shuffle network using synthetic aperture radar imagery

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    Synthetic Aperture Radar (SAR) imagery can be beneficial for segmenting oil spills, which are a common environmental hazard. Oil spill detection in SAR imagery faces several challenges, including speckle noise, heterogeneous backgrounds, blurred edges, and a lack of comprehensive datasets with multiple images. ShuffleNet is one of the deep networks, which has never been used for oil spill segmentation. In this article, ShuffleNet blocks are used to detect oil spills in SAR images, which is more effective than other methods. Besides, the main network design, six other blocks were evaluated, and the most valuable one was selected. We use group convolutions, shuffle channels, and atrous convolutions in this model with a minimum number of layers of ReLU. The methods are evaluated based on the Intersection Over Union (IoU) parameter so that the proposed method improved the mIoU by 7.1% over the best results of some previous methods

    Effect Of Zinc Oxide RF Sputtering Pressure on the Structural and Optical Properties of ZnO/PEDOT:PSS Inorganic/Organic Heterojunction

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    Zinc oxide nanostructures are deposited on glass substrates in the presenceof oxygen reactive gas at room temperature using the radio frequency magnetronsputtering technique. In this research, the effects of zinc oxide sputtering pressure on thenanostructure properties of the deposited layer are investigated. The deposition pressurevaries from 7.5 to 20.5 mTorr. AFM results show that with an increase in the depositionpressure, the grain size increases and the surface roughness decreases. The energy gapmeasured for the zinc oxide layers deposited at the pressures of 7.5, 14 and 20.5 mTorrwas 3.26, 3.18, and 3.19 eV, respectively. In order to investigate the junction betweenzinc oxide and poly (3, 4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS),a polymeric layer of thickness of 50 nm is deposited on a 300 nm zinc oxide layer byspin coating technique. The dark I-V characteristics indicate that the reverse saturationcurrent density is 1.82 10-6, 1.96 10-7 and 7.58 10-8 A/cm2 for the depositionpressures of 7.5, 14, and 20.5 mTorr, respectively. By increasing the deposition pressurethe ideality factor of the resulting Schottky barrier dropped from 3.4 to 1.7. Theeffective Schottky barrier height of 0.73, 0.78, and 0.81 eV was obtained for the sameorder of deposition pressures. It was found that the highest optical response could beobtained for the samples deposited at the deposition pressure of 14 mTorr.

    A high precision logarithmic-curvature compensated all CMOS voltage reference

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    This paper presents a resistor-less high-precision, sub-1 V all-CMOS voltage reference. A curvature-compensation method is used to cancel the logarithmic temperature dependence regardless of mobility temperature exponent (γ). The circuit is simulated in 65 nm CMOS technology and yields an output voltage of 594 mV, temperature coefficient of 7ppm∘C in the range of −40 to 125 °C, a power supply rejection ratio (PSRR) of − 43 dB at of 100 Hz, a line sensitivity of 76μVV in the supply voltage range of 1.2 to 2 V, a power dissipation of 1.4μW at 1.2 V supply and an output noise of 2.8μVHz at 100Hz. The total active area of the design is 0.03mm2. This voltage reference is suitable for low-power, low-voltage applications which also require high precision

    An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS

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    In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent (γ). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 ppm∘C in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of 6μVV in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 μV/Hz at 100 Hz. The total active area of the design is 0.03 mm2. This voltage reference is suitable for low-power low-voltage applications which also require high precision
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