Charged basal stacking fault (BSF) scattering in nitride semiconductors

A theory of charge transport in semiconductors in the presence of basal stacking faults is developed. It is shown that the presence of basal stacking faults leads to anisotropy in carrier transport. The theory is applied to carrier transport in non-polar GaN films consisting of a large number BSFs, and the result is compared with experimental data.Comment: 4 pages, 3 figure

Tailoring the carrier mobility of semiconducting nanowires by remote dielectrics

The dielectric environment of thin semiconductor nanowires can affect the charge transport properties inside the wire. In this work, it is shown that Coulomb impurity scattering inside thin nanowires can be damped strongly by coating the wire with a high-k dielectric. This will lead to an increase in the mobility of free charges inside the wire.Comment: 4 pages, 3 figure

Effect of high-K dielectrics on charge transport in graphene

The effect of various dielectrics on charge mobility in single layer graphene is investigated. By calculating the remote optical phonon scattering arising from the polar substrates, and combining it with their effect on Coulombic impurity scattering, a comprehensive picture of the effect of dielectrics on charge transport in graphene emerges. It is found that though high-$\kappa$ dielectrics can strongly reduce Coulombic scattering by dielectric screening, scattering from surface phonon modes arising from them wash out this advantage. By comparing the room-temperature transport properties with narrow-bandgap III-V semiconductors, strategies to improve the mobility in single layer graphene are outlined.Comment: 6 pages, 4 Figure

Carrier Statistics and Quantum Capacitance of Graphene Sheets and Ribbons

In this work, fundamental results for carrier statistics in graphene 2-dimensional sheets and nanoscale ribbons are derived. Though the behavior of intrinsic carrier densities in 2d graphene sheets is found to differ drastically from traditional semiconductors, very narrow (sub-10 nm) ribbons are found to be similar to traditional narrow-gap semiconductors. The quantum capacitance, an important parameter in the electrostatic design of devices, is derived for both 2d graphene sheets and nanoribbons.Comment: 3 pages, 3 figures, submitted to Applied Physics Letter

Enhancement of Carrier Mobility in Semiconductor Nanostructures by Dielectric Engineering

We propose a technique for achieving large improvements in carrier mobilities in 2- and 1-dimensional semiconductor nanostructures by modifying their dielectric environments. We show that by coating the nanostructures with high-$\kappa$ dielectrics, scattering from Coulombic impurities can be strongly damped. Though screening is also weakened, the damping of Coulombic scattering is much larger, and the resulting improvement in mobilities of carriers can be as much as an order of magnitude for thin 2D semiconductor membranes, and more for semiconductor nanowires.Comment: 5 Pages, 4 Figure

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.Comment: 22 pages, 5 Figures, Nano Letter