Distributed Arithmetic FPGA Design with Online Scalable Size and Performance

The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with di#erent performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages

Operating Systems for FPGA Based Computers and Their Memory Management

We introduce the concept of an operating system for platforms that consist beside memory and peripheral devices of FPGAs as the only computational resource

Memory Management to Support Multitasking on FPGA Based Systems

This work targets platforms, which consist beside memory and peripheral devices of FPGAs as the only computational resource

Periodic Real-Time Scheduling for FPGA Computers

Todays reconfigurable hardware devices, such as FPGAs, have high densities and allow for the execution of several hardware tasks in parallel. This paper deals with scheduling periodic real-time tasks to such an architecture, a problem which has not been considered before. We formalize the real-time scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known Earliest Deadline First (EDF) technique to the FPGA execution model. The algorithm reveals good scheduling performance; task sets with system utilizations of up to 85% can be feasibly scheduled. However, the EDF approach is practical only for a small number of tasks, since there is no efficient schedulability test. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method can only feasibly schedule task sets with a system utilization of up to some 50%, it is applicable to large tasks sets as the schedulability test runs in polynomial time. Equally important, the method requires only a small number of FPGA configurations which directly translates into reduced memory requirements

A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware

This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known Earliest Deadline First (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations

Off-Line Placement of Tasks onto Reconfigurable Hardware Considering Geometrical Task Variants

We consider o#-line task placement onto reconfigurable hardware devices (RHDs), which are increasingly used in embedded systems. The tasks are modelled as three dimensional boxes given by their footprint times execution time which results into a three dimensional orthogonal packing problem. Unlike other approaches, we allow several alternative implementation variants for each task, which enables better placements. We apply modified heuristic methods from chip floorplanning to select and place the task variants. Our method computes a set of pareto placement solutions with the objectives to minimize the total execution time and the amount of required RHD area. We have evaluated the placement quality in first simulation experiments

Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis

This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA

Memory-demanding Periodic Real-Time Applications on FPGA Computers

This paper presents work in progress on executing realtime applications on FPGA-based computing systems. Usually, these systems provide an FPGA device coupled with multiple external SRAM banks. Todays FPGAs show large capacities and are reprogrammable during runtime, allowing for space- and time-sharing multitasking. Typical FPGA tasks demand large memory buffers and access them periodically. In our previous work, we have devised techniques for scheduling periodic real-time tasks to such systems. In this paper, we address the resulting problem of assigning data buffers to physical memories, and aim at minimizing the number of required memories for a given application. We model the minimization problem as an integer linear program and present first results

Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System

Static FPGA (Field Programmable Gate Arrays) designs are efficient for data flow oriented applications while they are inefficient for control flow. We show that partial dynamic reconfigured designs can be more efficient than static designs, if the application contains exclusive coarse grain sections. Our case study is a multi-controller system, where various controller modules are exchanged during runtime depending on the operating regime of the controlled system. We present a multi-controller architecture as embedded system based on reconfigurable hardware. Portions of the FPGA design are exchanged during runtime to load new controller modules while other portions containing basic operational functions are static. We implemented a prototype to proof the concept and discuss the results