Advanced thermal simulation of SiGe:C HBTs including back-end-of-line

Advanced 3-D thermal simulations of state-of-the-art SiGe:C HBTs are performed, which ensure improved accuracy with respect to conventional approaches. The whole back-end-of-line architecture is modeled so as to account for the cooling effect due to the upward heat flow. Moreover, a nonuniform power density is considered to describe the heat source, and thermal conductivity degradation effects due to germanium, doping profile, and phonon scattering in narrow layers are implemented. The numerical thermal resistances are compared with those experimentally evaluated by means of a robust technique relying on the temperature dependence of the base-emitter voltage

Experimental DC extraction of the base resistance of bipolar transistors: Application to SiGe:C HBTs

This paper presents an improved variant of a dc method to experimentally evaluate the base resistance of a bipolar transistor. The technique relies on a device model associated with a simple parameter optimization methodology, and is suited for modern technologies wherein self-heating and impact-ionization effects play a relevant role. The approach is successfully applied to state-of-the-art SiGe:C heterojunction bipolar transistors for high-frequency applications, although it can in principle be exploited for any bipolar device. The accuracy of the method is verified by numerical and experimental procedure

Efficient Millimeter Wave Doherty PA Design Based on a Low-Loss Combiner Synthesis Technique

We report on a record-efficient 30-GHz 21-dBm differential Doherty PA designed in a 130-nm SiGe process. The output network is designed using a recently developed combiner synthesis technique. This technique enables impedance inversion and parasitic compensation to be integrated in one compact network. As a result, the combiner loss is reduced with 0.3-0.5 dB compared with a conventional Doherty combiner. The measured collector and power-added efficiencies at 6-dB back-off level are 30% and 24.3%, respectively, which further validates the advantages of the design technique

Influence of scaling and emitter layout on the thermal behavior of toward-THz SiGe:C HBTs

An extensive on-wafer experimental campaign is carried out to determine the thermal resistance dependence on scaling and emitter geometry in state-of-the-art toward-THz silicon–germanium bipolar transistors designed and fabricated within the framework of the European DOTFIVE project. The extraction is performed through a robust procedure, which—differently from classic approaches—exploits an accurately calibrated thermometer relating base-emitter voltage to junction temperature. Experimental data are then used to assess the accuracy of scalable thermal resistance laws for advanced transistor models; it was found that at least four parameters are needed to ensure a favorable agreement over wide ranges of emitter widths and length