29 research outputs found
A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC
The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with
extended dynamic range is presented, for use in the readout electronics upgrade
for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The
design consists of two pipeline A/D channels with four Multiplying
Digital-to-Analog Converters with nominal 12-bit resolution each. The design,
fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at
18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5
V supply, and exhibits no performance degradation after irradiation. Various
gain selection algorithms to achieve the extended dynamic range are implemented
and tested.Comment: 22 pages, 22 figures, accepted by JINS
A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC
The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at
the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a
radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is
presented. The design consists of two pipeline A/D channels each with four
Multiplying Digital-to-Analog Converters followed by 8-bit
Successive-Approximation-Register analog-to-digital converters. The custom
design, fabricated in a commercial 130 nm CMOS process, shows a performance of
67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5
ns (to first bit read out), while its total power consumption is 50 mW/channel.
The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to
single event effects during irradiation is measured and determined to meet the
system requirements
How Tiny Can Analog Filterbank Features Be Made for Ultra-low-power On-device Keyword Spotting?
Analog feature extraction is a power-efficient and re-emerging signal
processing paradigm for implementing the front-end feature extractor in on
device keyword-spotting systems. Despite its power efficiency and re-emergence,
there is little consensus on what values the architectural parameters of its
critical block, the analog filterbank, should be set to, even though they
strongly influence power consumption. Towards building consensus and
approaching fundamental power consumption limits, we find via simulation that
through careful selection of its architectural parameters, the power of a
typical state-of-the-art analog filterbank could be reduced by 33.6x, while
sacrificing only 1.8% in downstream 10-word keyword spotting accuracy through a
back-end neural network.Comment: Accepted as a full paper by the TinyML Research Symposium 202
Project-based Learning within a Large-Scale Interdisciplinary Research Effort
The modern engineering landscape increasingly requires a range of skills to
successfully integrate complex systems. Project-based learning is used to help
students build professional skills. However, it is typically applied to small
teams and small efforts. This paper describes an experience in engaging a large
number of students in research projects within a multi-year interdisciplinary
research effort. The projects expose the students to various disciplines in
Computer Science (embedded systems, algorithm design, networking), Electrical
Engineering (circuit design, wireless communications, hardware prototyping),
and Applied Physics (thin-film battery design, solar cell fabrication). While a
student project is usually focused on one discipline area, it requires
interaction with at least two other areas. Over 5 years, 180 semester-long
projects have been completed. The students were a diverse group of high school,
undergraduate, and M.S. Computer Science, Computer Engineering, and Electrical
Engineering students. Some of the approaches that were taken to facilitate
student learning are real-world system development constraints, regular
cross-group meetings, and extensive involvement of Ph.D. students in student
mentorship and knowledge transfer. To assess the approaches, a survey was
conducted among the participating students. The results demonstrate the
effectiveness of the approaches. For example, 70% of the students surveyed
indicated that working on their research project improved their ability to
function on multidisciplinary teams more than coursework, internships, or any
other activity
An Analog Neural Computer with Modular Architecture for Real-Time Dynamic Computations
The paper describes a multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2µm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications have been tested successfully. Results of a network for real-time decomposition of acoustical patterns will be discussed