A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.published_or_final_versio

The DFA/DFT‐based hacking techniques and countermeasures: Case study of the 32‐bit AES encryption crypto‐core

Abstract Integrated circuits (ICs) design plays a significant role in the embedded‐system performance, reliability and security. Thus, the constant advances in very large‐scale integration technology have led to design and manufacture of very complex ICs based on the System on a Chip (SoC) approach design. Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety‐critical embedded system designs. On the other hand, embedded systems used in critical applications execute security‐critical commands and collect sensitive data protected by cryptographic keys and authentication codes. The data and the unauthorised access of these embedded devices is an obvious target for attackers in order to obtain control or extract internal data. In this paper we consider that by using Design for Testability (DFT) approaches an attacker can control and affect a security‐critical embedded system. Thus, the authors focus on the DFT approach, as a means of violation of the security and confidentiality of embedded systems with security‐critical goals. In addition, with or without insertion of DFT circuitry, the crypto‐core is always exposed to the powerful differential fault analysis (DFA) attack. Here, a 32‐bit AES crypto‐core is used as a case study in order to analyse the DFA‐ and the DFT‐based Hacking techniques. A countermeasure was performed in order to avoid any scan or even DFA attack attempt

Design of a Reliable XOR-XNOR Circuit for Arithmetic Logic Units

Part 12: DATICSInternational audienceComputer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology

A Self-test and self-repair approach for analog integrated circuits

With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence of soft and hard faults. Thus, testing has become a real challenge for enhancing the reliability of safety-critical systems. This paper presents a Self-Test and Self- Repair approach which can be used to tolerate the most likely defects of bridging type that create a resistive path between VDD supply voltage and the ground occurring in analog CMOS circuits during the manufacturing process. The proposed testing approach is designed using the 65 nm CMOS technology. We then used an operational amplifier (OPA) to validate the technique and correlate it with post layout simulation resultsTaikomosios informatikos katedraVytauto Didžiojo universiteta