7 research outputs found
Reinventing Integrated Photonic Devices and Circuits for High Performance Communication and Computing Applications
The long-standing technological pillars for computing systems evolution, namely Moore\u27s law and Von Neumann architecture, are breaking down under the pressure of meeting the capacity and energy efficiency demands of computing and communication architectures that are designed to process modern data-centric applications related to Artificial Intelligence (AI), Big Data, and Internet-of-Things (IoT). In response, both industry and academia have turned to \u27more-than-Moore\u27 technologies for realizing hardware architectures for communication and computing. Fortunately, Silicon Photonics (SiPh) has emerged as one highly promising ‘more-than-Moore’ technology. Recent progress has enabled SiPh-based interconnects to outperform traditional electrical interconnects, offering advantages like high bandwidth density, near-light speed data transfer, distance-independent bitrate, and low energy consumption. Furthermore, SiPh-based electro-optic (E-O) computing circuits have exhibited up to two orders of magnitude improvements in performance and energy efficiency compared to their electronic counterparts. Thus, SiPh stands out as a compelling solution for creating high-performance and energy-efficient hardware for communication and computing applications. Despite their advantages, SiPh-based interconnects face various design challenges that hamper their reliability, scalability, performance, and energy efficiency. These include limited optical power budget (OPB), high static power dissipation, crosstalk noise, fabrication and on-chip temperature variations, and limited spectral bandwidth for multiplexing. Similarly, SiPh-based E-O computing circuits also face several challenges. Firstly, the E-O circuits for simple logic functions lack the all-electrical input handling, raising hardware area and complexity. Secondly, the E-O arithmetic circuits occupy vast areas (at least 100x) while hardly achieving more than 60% hardware utilization, versus CMOS implementations, leading to high idle times, and non-amortizable area and static power overheads. Thirdly, the high area overhead of E-O circuits hinders them from achieving high spatial parallelism on-chip. This is because the high area overhead limits the count of E-O circuits that can be implemented on a reticle-size limited chip. My research offers significant contributions to address the aforementioned challenges. For SiPh-based interconnects, my contributions focus on enhancing OPB by mitigating crosstalk noise, addressing the optical non-linearity-related issues through the development of Silicon-on-Sapphire-based photonic interconnects, exploring multi-level signaling, and evaluating various device-level design pathways. This enables the design of high throughput (\u3e1Tbps) and energy-efficient (\u3c1pJ/bit) SiPh interconnects. In the context of SiPh-based E-O circuits, my contributions include the design of a microring-based polymorphic E-O logic gate, a hybrid time-amplitude analog optical modulator, and an indium tin oxide-based silicon nitride microring modulator and a weight bank for neural network computations. These designs significantly reduce the area overhead of current E-O computing circuits while enhancing the energy-efficiency, and hardware utilization
A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator
The use of the Silicon-on-Insulator (SOI) platform has been prominent for
realizing CMOS-compatible, high-performance photonic integrated circuits
(PICs). But in recent years, the silicon-nitride-on-silicon-dioxide
(SiN-on-SiO) platform has garnered increasing interest as an alternative to
the SOI platform for realizing high-performance PICs. This is because of its
several beneficial properties over the SOI platform, such as low optical
losses, high thermo-optic stability, broader wavelength transparency range, and
high tolerance to fabrication-process variations. However, SiN-on-SiO based
active devices such as modulators are scarce and lack in desired performance,
due to the absence of free-carrier based activity in the SiN material and the
complexity of integrating other active materials with SiN-on-SiO platform.
This shortcoming hinders the SiN-on-SiO platform for realizing active PICs.
To address this shortcoming, we demonstrate a SiN-on-SiO microring
resonator (MRR) based active modulator in this article. Our designed MRR
modulator employs an Indium-Tin-Oxide (ITO)-SiN-ITO thin-film stack, in which
the ITO thin films act as the upper and lower claddings of the SiN MRR. The
ITO-SiN-ITO thin-film stack leverages the free-carrier assisted, high-amplitude
refractive index change in the ITO films to effect a large electro-refractive
optical modulation in the device. Based on the electrostatic, transient, and
finite difference time domain (FDTD) simulations, conducted using photonics
foundry-validated tools, we show that our modulator achieves 280 pm/V resonance
modulation efficiency, 67.8 GHz 3-dB modulation bandwidth, 19 nm
free-spectral range (FSR), 0.23 dB insertion loss, and 10.31 dB
extinction ratio for optical on-off-keying (OOK) modulation at 30 Gb/s
SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs
The acceleration of a CNN inference task uses convolution operations that are
typically transformed into vector-dot-product (VDP) operations. Several
photonic microring resonators (MRRs) based hardware architectures have been
proposed to accelerate integer-quantized CNNs with remarkably higher throughput
and energy efficiency compared to their electronic counterparts. However, the
existing photonic MRR-based analog accelerators exhibit a very strong trade-off
between the achievable input/weight precision and VDP operation size, which
severely restricts their achievable VDP operation size for the quantized
input/weight precision of 4 bits and higher. The restricted VDP operation size
ultimately suppresses computing throughput to severely diminish the achievable
performance benefits. To address this shortcoming, we for the first time
present a merger of stochastic computing and MRR-based CNN accelerators. To
leverage the innate precision flexibility of stochastic computing, we invent an
MRR-based optical stochastic multiplier (OSM). We employ multiple OSMs in a
cascaded manner using dense wavelength division multiplexing, to forge a novel
Stochastic Computing based Optical Neural Network Accelerator (SCONNA). SCONNA
achieves significantly high throughput and energy efficiency for accelerating
inferences of high-precision quantized CNNs. Our evaluation for the inference
of four modern CNNs at 8-bit input/weight precision indicates that SCONNA
provides improvements of up to 66.5x, 90x, and 91x in frames-per-second (FPS),
FPS/W and FPS/W/mm2, respectively, on average over two photonic MRR-based
analog CNN accelerators from prior work, with Top-1 accuracy drop of only up to
0.4% for large CNNs and up to 1.5% for small CNNs. We developed a
transaction-level, event-driven python-based simulator for the evaluation of
SCONNA and other accelerators (https://github.com/uky-UCAT/SC_ONN_SIM.git).Comment: To Appear at IPDPS 202
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits
In the wake of dwindling Moore's law, integrated electro-optic (E-O) computing circuits have shown revolutionary potential to provide progressively faster and more efficient hardware for computing. The E-O circuits for computing from the literature can operate with minimal latency at high bit-rates. However, they face shortcomings due to their operand handling complexity, non-amortizable high area and static power overheads, and general unsuitability for large-scale integration on reticle-limited chips. To alleviate these shortcomings, in this paper, we present a microring resonator (MRR) based polymorphic E-O logic gate (MRR-PEOLG) that can be dynamically programmed to implement different logic functions at different times. Our MRR-PEOLG can provide compactness and polymorphism to E-O circuits, to consequently improve their operand handling and amortization of area and static power overheads. We model our MRR-PEOLG using photonics foundry-validated tools to perform frequency and time-domain analysis of its polymorphic logic functions. Our evaluation shows that the use of our MRR-PEOLG in two E-O circuits from prior works can reduce their area-energy-delay product by up to 82.6. A tutorial on the modeling and simulation of our MRR-PEOLG, along with related codes and files, is available on https://github.com/uky-UCAT/MRR-PEOLG