First functionality tests of a 64 x 64 pixel DSSC sensor module connected to the complete ladder readout

The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV - 6keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128 x 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64 x 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain.Comment: Preprint proceeding for IWORID 2016, 18th International Workshop on Radiation Imaging Detectors, 3rd-7th July 2016, Barcelona, Spai

A 64-by-64 pixel-ADC matrix

An 8-bit 5-MS/s Wilkinson-type analog-to-digital converter (ADC) cell has been designed for parallel in-pixel digitization in a 64-by-64 pixel readout ASIC. Due to its simplicity, low power consumption, and small area requirement this type of ADC is suitable for pixel-level implementations. 720-ps time stamps are generated globally by means of 8-bit Gray-code counters. They are distributed column-wise to the pixel blocks together with a conversion-start signal along 13-mm long transmission lines. The analog input voltage is sampled-and-held on a capacitor. A pixel-internal current source is used to generate a voltage ramp. The conversion into a digital word is done when the ramp voltage equals the reference voltage, and the corresponding time stamp is latched. The ASIC is fabricated in IBM's 130-nm CMOS technology. The pixel-wise gain trimming properties provide a homogeneous gain distribution. Full matrix measurements demonstrate the achievement of a signal-to-noise ratio of 70 dB when all 4096 ADCs are working simultaneously. 75 % of the pixels show DNL better than 0.4 LSB, and the INL remains within ± 0.5 LSB for 99% of the pixels. The area and power dissipation of the in-pixel ADC amounts to 100 × 120 μm2 and 150 μW at 1.2-V power supply, respectively

First functionality tests of a 64 x 64 pixel DSSC sensor module connected to the complete ladder readout

The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV - 6keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128 x 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64 x 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain

A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between 250eV and 6keV , and must provide a peak frame rate of 4.5MHz to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring 512×128 hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at 18°C . An outstanding equivalent noise charge of 9.8 e−rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV (ADU/keV). At 4.5MHz and 3.1ADU/keV , a noise of 25.5 e−rms and a dynamic range of 26ke- are obtained. The highest dynamic range of 1.345Me- is reached at 2.25MHz and 1.6ADU/keV . These values can fulfill the specification of the DSSC projec

A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between 250eV and 6keV, and must provide a peak frame rate of 4.5MHz to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring 512×128 hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at 18°C. An outstanding equivalent noise charge of 9.8 e⁻rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV (ADU/keV). At 4.5MHz and 3.1 ADU/keV, a noise of 25.5 e⁻rms and a dynamic range of 26 ke⁻ are obtained. The highest dynamic range of 1.345 Me⁻ is reached at 2.25 MHz and 1.6 ADU/keV. These values can fulfill the specification of the DSSC project

First operation of a DSSC hybrid 2D Soft X-ray imager with 4.5 MHz frame rate

The DSSC (DEPFET Sensor with Signal Compression) collaboration develops a hybrid pixelated X-Ray photon detector with 4.5 MHz frame rate and immediate amplitude digitization for experiments at the European XFEL. We present the first full format 14.9Ã\u9714 mm2F1 pixel readout ASIC for the DSSC detector. The readout architecture is specially adapted to the burst structure of the XFEL (bursts of 2880 pulses spaced by down to 220 ns at a rate of 10 Hz) by in-pixel digitization and digital hit data storage and data transfer during the burst gaps. The readout ASIC contains 64Ã\u9764 pixels of 229Ã\u97204 μm2size and includes per pixel two low noise front-end versions for DEPFET and silicon drift detectors (SDD), a single-slope 8-bit ADC and local memory. Measurements using the F1 ASIC and a matching mini-SDD sensor matrix are shown

The DSSC Pixel Readout ASIC with Amplitude Digitization and Local Storage for DEPFET Sensor Matrices at the European XFEL

The DSSC (DEPFET Sensor with Signal Compression) consortium develops a 1MPixel detector for low energy X-rays at the European XFEL. The XFEL will produce 10 bursts per second, each containing 2880 X-ray pulses with a repetition rate of 4.5 MHz. X-ray photons of 0.5 − 6 keV are absorbed in hexagonal DEPFET pixels of 229x204 um^2 pitch with a nonlinear characteristic to achieve a high dynamic range. The sensors will be bump bonded to readout ASICs of 64x64 pixels. Each pixel contains a filter with trapezoidal weighting function, a single slope ADC of 8-9 Bit resolution and a digital memory to store 640 events. A veto mechanism allows to discard uninteresting events. The digital hit data is read out serially during the ≈ 100 ms long burst gaps. Prototype matrix chips of 8x8 pixels with the full functionality have been produced and characterized electronically and with DEPFET sensors. The architecture and the design of the 8x8 ASIC, measured results and an outlook to the large 64x64 pixel chip will be presented