Secure Scan Design with a Novel Methodology of Scan Camouflaging

Scan based attacks are the major security concerns of a design. These attacks are majorly employed to understand the camouflaged logic during reverse engineering. The state-of-the-art techniques like scan chain scrambling hinder accessibility of scan chains, but are prone to layout level reverse engineering attacks. In the proposed methodology, the scan design is secured by adding an extra scan input port (DSI) to the flipflop using dummy contacts, which ensure that DSI cannot be distinguished from SI port even with layout based reverse engineering techniques. Dummy scan chain connections are introduced in the design by connecting DSI port to the nearby flipflop Q output port. Our proposed method can withstand Reset-and-scan attack, Incremental SAT-based attack and the recent ScanSAT attack. The performance of this concept is measured in terms of frequency and total power consumption on IWLS-2005 benchmark circuits having up to 1380 flipflops with 40nm technology library. The delay is effected by a maximum of 2.2% with 50% obfuscation without any impact on power, pattern generation time and scan test time

IC age estimation methodology using IO pad protection diodes for prevention of Recycled ICs

Recycled ICs have become a major threat to the ICs used in safety critical systems. In the current state-of-the-art techniques, recycled ICs are detected by measuring the frequency, current, path delay or power-up values to estimate the HCI, BTI and EM effects on the transistors with age. Some of the state-of-the-art techniques require additional on-chip sensors to detect and estimate the age of an IC while others use existing logic like SRAM and Flip-flops to detect the recycled ICs. In this paper, we provide a methodology to detect a recycled IC and also to estimate its age by using the existing IO pad structures. For the first time, age is estimated by measuring voltage drop across the protection diodes present in IO pad structure. With this methodology, no additional sensors have to be added and hence there is no area overhead. With this proposed methodology, ICs that are used for a minimum period of a day can be effectively detected by using the concept of extended Kalman filtering technique for the first time in this domain. By stressing the part for five days, our proposed methodology can estimate the age of the IC aged between 1 month to 5 years with 95% percent of accuracy. © 2021 IEE

Modeling Attacks Resilient Multiple PUF-CPRNG Architecture Design Methodology

In the present scenario of cryptographic protocols, Physical Unclonable Functions(PUF) is regarded as the primary primitive due to its properties like uniqueness, robustness, unclonability, and unpredictability which makes a system more secure random number generators for light-weight security applications. In this paper we are proposing a PUF based chaotic pseudo random number generator as Multiple PUF-CPRNG, which is more resilient to state-of-the-art modeling attacks like Logistic Regression, Becker Attack and Deep Neural Network. On comparing with other PUF based architecture like XOR-Arbiter PUF, Double Arbiter PUF (DAPUF) and Ring Oscillator PUF-CPRNG structure, the proposed architecture is more resilient to the above mentioned attacks. In this paper, accuracy of the predicting response bits of the proposed structure has been reduced with at least 3% in comparison to the state-of-the-art PUF architectures. While comparing with the hardware complexity we are reducing more than 5% in terms of FPGA resources. The proposed design also passed all 15 statistical randomness test described in NIST 800-22 Test Suite. © 2022 IEEE

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis