Performance for cryptography: Ahardware approach

Cryptography can be considered as a special application of coding schemes. High speed execution of Encoding and Decoding processes is crucial in the majority of the so-called security schemes. In fact, the characteristics of a cryptographic algorithm in terms of throughput are usually the most important requirement to adopt the algorithm in a security scheme. As the need for higher security increases, the market urges for strong cryptographic protocols that will offer the desired degree of privacy. However, most of the algorithms now and forthcoming are complex and do not seem to be efficient for performance-oriented purposes. In this chapter, an algorithmic approach for designing high-speed cryptographic primitives is presented. Setting as target the high throughput, a complete methodology for developing various types of cryptographic primitives, focusing on hardware (without however excluding software, or a combination of them) is offered. The application of the proposed design approach also highlights the effect of designing for supercomputing on a critical application, such as cryptography. Parallelism and code transformation are few of the techniques that will be used for achieving the desired target, the implementation of the ever best proposed cryptographic primitives in terms of speed and throughput. © 2009 Nova Science Publishers, Inc. All rights reserved

Intrusion Detection and Botnet Prevention Circuit for IoT Devices

The need for secure and trustworthy devices has become the main question in the Internet of Things market nowadays. This work aims to introduce a circuit connected inline to the device's power supply and analyze its behavior. The detection circuit operates in real time (Real Time detection), i.e. it collects the information by reading the values of the current intensity from the device and processes it for the detection of abnormal activities. Exploiting side-channel attack techniques, the circuits detect any anomaly of the expected operation and quarantines the device under monitoring. The circuit is analyzed and a simple implementation is depicted. The results of the circuit's test showed excellent efficiency in intrusion detection, with a 100% success. © 2020 IEEE

A power dissipation monitoring circuit for intrusion detection and botnet prevention on iot devices

Recently, there has been a sharp increase in the production of smart devices and related networks, and consequently the Internet of Things. One concern for these devices, which is constantly becoming more critical, is their protection against attacks due to their heterogeneity and the absence of international standards to achieve this goal. Thus, these devices are becoming vulnerable, with many of them not even showing any signs of malfunction or suspicious behavior. The aim of the present work is to introduce a circuit that is connected in series with the power supply of a smart device, specifically an IP camera, which allows analysis of its behavior. The detection circuit operates in real time (real-time detection), sampling the supply current of the device, processing the sampled values and finally indicating any detection of abnormal activities, based on a comparison to normal operation conditions. By utilizing techniques borrowed by simple power analysis side channel attack, it was possible to detect deviations from the expected operation of the IP camera, as they occurred due to intentional attacks, quarantining the monitored device from the rest of the network. The circuit is analyzed and a low-cost implementation (under 5US$) is illustrated. It achieved 100% success in the test results, showing excellent performance in intrusion detection. © 2020 by the authors. Licensee MDPI, Basel, Switzerland

Efficient high-performance ASIC implementation of JPEG-LS encoder

This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The proposed implementation consists of an efficient pipelined JPEG-LS encoder, which operates at a significantly higher encoding rate than any other JPEG-LS hardware or software implementation while keeping area small. © 2007 EDAA

Speeded up and low-powered hardware implementation of the secure hash algorithm through partial unrolling

Applications that call for data integrity and signature authentication at electronic transactions invoke cryptographic primitives like hash functions. A hash function is utilized in the security layer of every communication protocol. However, as protocols evolve and new high-performance applications appear, the throughput of hash functions seems to reach to a limit. Market is asking for new implementations with higher throughputs respecting the tendency of the market to minimize devices' size and increase their autonomy to make them portable. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new a partially unrolled implementation is presented that comes to exceed this limit improving the throughput by 53%. Power issues have also been taken in consideration, in such way that the proposed implementation can be characterized as low-power

A Tetris-based legalization heuristic for standard cell placement with obstacles

Legalization techniques are used both as a final stage and potentially as part of an iterative process of a global cell placement algorithm that distributes cells over a chip area in order to optimize criteria such as wirelength, routability, thermal dissipation etc. Although very efficient dynamic programming algorithms exist for standard cell placement legalization they usually incur high computational complexity, thus, might not be appropriate for acting as subcomponents in an iterative global placement process. On the other hand fast, single pass approaches such as Tetris heuristic, may offer low performance in terms of final placement quality. In this paper we turn our attention to legalization in standard cell placement under the presence of obstacles, with the aim of developing a fast yet efficient solution for the problem. The proposed heuristic is based on Tetris and involves judicious chip area splitting. Experiments with ibm circuits demonstrate that the resulting scheme, called OBstacle-aware Area Splitting Tetris (OBAST), offers significant performance improvement both in terms of solution quality and running time. © 2018 IEEE

Success stories from consumer technology-helping and saving lives

Consumer technology (CT) has a broad amount of fields of application, among which one of the most important ones is represented by healthcare and well-being. Thanks to the quick technological development of ICT, CT have become widespread throughout the citizenship, allowing one to easily self-monitor his/her physiological parameters, checking for eventually dangerous values that could require the assistance from a medical doctor or caregiver. This panel session aims at presenting some CT solutions supporting healthcare during the life cycle of an individual, from early days until later life, providing hints about some of the possible conditions representing the major threats to healthy life throughout the years. © 2021 IEEE

Survey on Routing Services for Smart Delivery in Urban Environments

The problems of routing in cities are examined in this survey and highlight key points that need to be considered for smart delivery, which is time-restricted and cost-effective. Smart cities require smart services and applications to deal with their routing problems. This paper provides a brief classification of the route planning algorithms and a taxonomy of the routing problems and existing services. Taking into consideration issues related to time, cost, destination, temporal penalties during operations, and other parameters, a survey for solving a multi-objective routing problem is offered. The survey concludes with a comparison of the most promising research solutions. © 2020 IEEE

Implementation of HSSec: A high-speed cryptographic co-processor

In this paper a high-speed cryptographic co-processor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used inevery system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family. © 2007 IEEE

Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Volume 3728, 2005, Pages 591-600Hash functions are widely used in applications that call for data integrity and signature authentication at electronic transactions. A hash function is utilized in the security layer of every communication protocol. As time passes more sophisticated applications arise that address to more users-clients and thus demand for higher throughput. Furthermore, due to the tendency of the market to minimize devices' size and increase their autonomy to make them portable, power issues have also to be considered. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new implementation comes to exceed this limit improving the throughput by 53%. Furthermore,power dissipation is kept low compared to previous works, in such way that the proposed implementation can be characterized as low-power. © Springer-Verlag Berlin Heidelberg 2005