EXTRA: Towards an efficient open platform for reconfigurable High Performance Computing

To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field

FGPU: a flexible soft GPU architecture for general purpose computing on FPGAs

Die Realisierung eingebetteter Grafikprozessoren (GPUs) auf Field Programmable Gate Arrays (FPGAs) führt zu einer neuen Prozessorfamilie, die die Effizienz und eine einfache Programmierung einer GPU ermöglicht, aber die Flexibilität und die Rekonfigurierbarkeit einer FPGA-Plattform nutzt. Diese Dissertation beschreibt den Entwurf der Hardware sowie das Tool Flows der FGPA-GPU (FGPU): eine konfigurierbare, skalierbare und portierbare GPU, die für FPGAs speziell entwickelt wurde. FGPU ist für universelles Rechnen auf GPUs (GPGPU) gedacht und sie repliziert keine andere Architektur. FGPU unterstützt Gleitkomma-Arithmetik in einfacher Genauigkeit in Hardware oder als emulierte Instruktionen in Software. Darüber hinaus wurde ein dedizierter Compiler auf Basis der LLVM Entwicklungsumgebung entworfen. FGPU kann über eine PYNQ-basierte Schnittstelle mit Python-Skripten programmiert und gesteuert werden

DynamIA: dynamic hardware reconfiguration in industrial applications

This paper presents the work that will be done in the research project “DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications”. The project focuses on transferring knowledge on partial and dynamic reconfiguration of FPGAs from the academic partners to small and medium enterprises (SMEs), because the success stories on partial and dynamic reconfiguration were mainly only realized in large companies with a substantial amount of R&D activities. The reason is that the technology is still perceived as being difficult to adopt and expensive in terms of NRE costs. Therefore, the goal of the DynamIA project is two-fold. (1) It develops a number of use cases and guidelines in different application domains, tailored to the activities of the SMEs in the user group and in the broader target group. These use cases demonstrate a number of benefits of partial and dynamic FPGA reconfiguration, namely a faster startup, a faster design cycle and a lower occupation of resources leading to a lower static power consumption. (2) It develops a low-cost, vendor-independent emulation environment for dynamic and partial reconfiguration, which is non-existing in commercial and academic EDA tools. Another benefit of this emulation environment is that it can also be used for static designs. This allows SMEs to have a low-cost emulation environment for their applications instead of developing their own emulation environment manually (which is very time-consuming) or buying big cost-intensive commercial emulators