Scalable Emulation of Sign-Problem-Free Hamiltonians with Room-Temperature p-bits

The growing field of quantum computing is based on the concept of a q-bit, which is a delicate superposition of 0 and 1, requiring cryogenic temperatures for its physical realization along with challenging coherent coupling techniques for entangling them. By contrast, a probabilistic bit or a p-bit is a robust classical entity that fluctuates between 0 and 1 and can be implemented at room temperature using present-day technology. Here, we show that a probabilistic coprocessor built out of room-temperature p-bits can be used to accelerate simulations of a special class of quantum many-body systems that are sign-problem-free or "stoquastic," leveraging the well-known Suzuki-Trotter decomposition that maps a d-dimensional quantum many-body Hamiltonian to a d+1-dimensional classical Hamiltonian. This mapping allows an efficient emulation of a quantum system by classical computers and is commonly used in software to perform quantum Monte Carlo (QMC) algorithms. By contrast, we show that a compact, embedded magnetic tunnel junction (MTJ)-based coprocessor can serve as a highly efficient hardware accelerator for such QMC algorithms, providing an improvement in speed of several orders of magnitude compared to optimized CPU implementations. Using realistic device-level spice simulations, we demonstrate that the correct quantum correlations can be obtained using a classical p-circuit built with existing technology and operating at room temperature. The proposed coprocessor can serve as a tool to study stoquastic quantum many-body systems, overcoming challenges associated with physical quantum annealers

Voltage-Driven Building Block for Hardware Belief Networks

Probabilistic spin logic (PSL), based on networks of binary stochastic neurons (or p-bits), has been shown to provide a viable framework for many functionalities including Ising computing, Bayesian inference, invertible Boolean logic and image recognition. This paper presents a hardware building block for the PSL architecture, consisting of an embedded MTJ and a capacitive voltage adder of the type used in neuMOS. We use SPICE simulations to show how identical copies of these building blocks (or weighted p-bits) can be interconnected with wires to design and solve a small instance of the NP-complete Subset Sum Problem fully in hardware

Correlated fluctuations in spin orbit torque coupled perpendicular nanomagnets

Low-barrier nanomagnets have attracted a great deal of research interest for their use as sources of high-quality true random number generation. More recently, low-barrier nanomagnets with tunable output have been shown to be a natural hardware platform for unconventional computing paradigms such as probabilistic spin logic. Efficient generation and tunability of high-quality random bits is critical for these novel applications. However, current spintronic random number generators are based on superparamagnetic tunnel junctions with tunability obtained through spin transfer torque, which unavoidably leads to challenges in designing concatenated networks using these two terminal devices. The more recent development of utilizing spin orbit torque (SOT) allows for a three-terminal device design, but can only tune in-plane magnetization freely, which is not very energy efficient due to the needs of overcoming a large demagnetization field. In this work, we experimentally demonstrate a stochastic device with perpendicular magnetic anisotropy that is completely tunable by SOT without the aid of any external magnetic field. Our measurements lead us to hypothesize that a tilted anisotropy might be responsible for the observed tunability. We carry out stochastic Landau-Lifshitz-Gilbert simulations to confirm our experimental observation. Finally, we build an electrically coupled network of two such stochastic nanomagnet-based devices and demonstrate that finite correlation or anticorrelation can be established between their output fluctuations by a weak interconnection, despite having a large difference in their natural fluctuation timescale. Simulations based on a dynamical model for autonomous circuits composed of low-barrier nanomagnets show close agreement with the experimental results

Correlated fluctuations in spin orbit torque coupled perpendicular nanomagnets

Low-barrier nanomagnets have attracted a great deal of research interest for their use as sources of high-quality true random number generation. More recently, low-barrier nanomagnets with tunable output have been shown to be a natural hardware platform for unconventional computing paradigms such as probabilistic spin logic. Efficient generation and tunability of high-quality random bits is critical for these novel applications. However, current spintronic random number generators are based on superparamagnetic tunnel junctions with tunability obtained through spin transfer torque, which unavoidably leads to challenges in designing concatenated networks using these two terminal devices. The more recent development of utilizing spin orbit torque (SOT) allows for a three-terminal device design, but can only tune in-plane magnetization freely, which is not very energy efficient due to the needs of overcoming a large demagnetization field. In this work, we experimentally demonstrate a stochastic device with perpendicular magnetic anisotropy that is completely tunable by SOT without the aid of any external magnetic field. Our measurements lead us to hypothesize that a tilted anisotropy might be responsible for the observed tunability. We carry out stochastic Landau-Lifshitz-Gilbert simulations to confirm our experimental observation. Finally, we build an electrically coupled network of two such stochastic nanomagnet-based devices and demonstrate that finite correlation or anticorrelation can be established between their output fluctuations by a weak interconnection, despite having a large difference in their natural fluctuation timescale. Simulations based on a dynamical model for autonomous circuits composed of low-barrier nanomagnets show close agreement with the experimental results

Neuromorphic spintronics

Neuromorphic computing uses basic principles inspired by the brain to design circuits that perform artificial intelligence tasks with superior energy efficiency. Traditional approaches have been limited by the energy area of artificial neurons and synapses realized with conventional electronic devices. In recent years, multiple groups have demonstrated that spintronic nanodevices, which exploit the magnetic as well as electrical properties of electrons, can increase the energy efficiency and decrease the area of these circuits. Among the variety of spintronic devices that have been used, magnetic tunnel junctions play a prominent role because of their established compatibility with standard integrated circuits and their multifunctionality. Magnetic tunnel junctions can serve as synapses, storing connection weights, functioning as local, nonvolatile digital memory or as continuously varying resistances. As nano-oscillators, they can serve as neurons, emulating the oscillatory behavior of sets of biological neurons. As superparamagnets, they can do so by emulating the random spiking of biological neurons. Magnetic textures like domain walls or skyrmions can be configured to function as neurons through their non-linear dynamics. Several implementations of neuromorphic computing with spintronic devices demonstrate their promise in this context. Used as variable resistance synapses, magnetic tunnel junctions perform pattern recognition in an associative memory. As oscillators, they perform spoken digit recognition in reservoir computing and when coupled together, classification of signals. As superparamagnets, they perform population coding and probabilistic computing. Simulations demonstrate that arrays of nanomagnets and films of skyrmions can operate as components of neuromorphic computers. While these examples show the unique promise of spintronics in this field, there are several challenges to scaling up, including the efficiency of coupling between devices and the relatively low ratio of maximum to minimum resistances in the individual devices

Autonomous probabilistic coprocessing with petaflips per second

In this article we present a concrete design for a probabilistic (p-) computer based on a network of p-bits, robust classical entities fluctuating between -1 and +1, with probabilities that are controlled through an input constructed from the outputs of other p-bits. The architecture of this probabilistic computer is similar to a stochastic neural network with the p-bit playing the role of a binary stochastic neuron, but with one key difference: there is no sequencer used to enforce an ordering of p-bit updates, as is typically required. Instead, we explore sequencerless designs where all p-bits are allowed to flip autonomously and demonstrate that such designs can allow ultrafast operation unconstrained by available clock speeds without compromising the solution's fidelity. Based on experimental results from a hardware benchmark of the autonomous design and benchmarked device models, we project that a nanomagnetic implementation can scale to achieve petaflips per second with millions of neurons. A key contribution of this article is the focus on a hardware metric - flips per second - as a problem and substrate-independent figure-of-merit for an emerging class of hardware annealers known as Ising Machines. Much like the shrinking feature sizes of transistors that have continually driven Moore's Law, we believe that flips per second can be continually improved in later technology generations of a wide class of probabilistic, domain specific hardware

The promise of spintronics for unconventional computing

Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/or stochasticity that spintronic devices can exhibit, and (iii) their compatibility with CMOS logic manufacturing processes. At the same time, the high endurance and speed of spintronic devices means that they can be rewritten or reconfigured frequently over the lifetime of a circuit, a feature that is essential in many emerging computing concepts. In this perspective, we will discuss how spintronics may aid in the realization of efficient devices, primarily focusing on magnetic tunnel junctions. We then provide a perspective on how these devices can impact the development of three unconventional computing paradigms, namely, reservoir computing, probabilistic computing and memcomputing. These paradigms may be used to address some limitations of modern computers, providing a realistic path to intelligent hybrid CMOS-spintronic systems

The promise of spintronics for unconventional computing

Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/or stochasticity that spintronic devices can exhibit, and (iii) their compatibility with CMOS logic manufacturing processes. At the same time, the high endurance and speed of spintronic devices means that they can be rewritten or reconfigured frequently over the lifetime of a circuit, a feature that is essential in many emerging computing concepts. In this perspective, we will discuss how spintronics may aid in the realization of efficient devices, primarily focusing on magnetic tunnel junctions. We then provide a perspective on how these devices can impact the development of three unconventional computing paradigms, namely, reservoir computing, probabilistic computing and memcomputing. These paradigms may be used to address some limitations of modern computers, providing a realistic path to intelligent hybrid CMOS-spintronic systems