Benchmarking mesh and hierarchical bus networks in system-on-chip context

Abstract. A simulation-based comparison scheme for on-chip communication networks is presented. Performance of the network depends heavily on the application and therefore several test cases are required. In this paper, generic synthesizable 2-dimensional mesh and hierarchical bus, which is an extended version of a single bus, are benchmarked in a SoC context with five parameterizable test cases. The results show that the hierarchical bus offers a good performance and area trade-off. In the presented test cases, a 2-dimensional mesh offers a speedup of 1.1x- 3.3x over hierarchical bus, but the area overhead is of 2.3x- 3.4x, which is larger than performance improvement.