SIP as a Universal Communication Bus: A Methodology and an Experimental Study

International audienceThis paper describes a methodology and a programming support that use the SIP protocol as a universal communication bus in pervasive computing environments. In doing so, our work enables homogeneous communications between heterogeneous distributed entities. We present a classification of a wide variety of entities in terms of features, capabilities and network connectors. Based on this classification, a methodology and a programming support are described for connecting entities on the SIP communication bus. This work has been validated by applications using the SIP communication bus to coordinate widely varying entities, including serial-based sensors (RS232, 1-Wire), ZigBee devices, X10 devices, PDA, native SIP entities, and software components

Créez et pilotez votre périphérique matériel sous Linux embarqué

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Créez simplement votre périphérique matériel avec le langage C

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IoT : programmez votre objet connecté RPi avec Python

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A SIP-based home Automation Platform: an experimental study

Abstract—SIP has demonstrated its effectiveness in enabling distributed entities to exchange any media using various interaction modes. In doing so, this protocol is showing great promise to support much extended forms of telecommunication services. This paper reports on the use of SIP as a communication middleware to support home automation applications that consist of heterogeneous, distributed entities. We describe how SIP fulfills the requirements of home automation; we present the resulting architecture of a home automation system; and, we validate our approach with various scenarios

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

International audienceIn this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution

Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel

La contribution de cette thèse concerne le développement et la conception d un système multimédia embarqué basé sur l approche de conception conjointe matérielle/logicielle (codesign). Il en résulte ainsi la constitution d une bibliothèque de modules IP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateforme matérielle de validation a été réalisée servant au préalable à l évaluation de l approche de conception en codesign pour l étude d algorithmes de traitement vidéo. Nous nous sommes ainsi intéressés en particulier à l étude et à l implantation de la norme de décompression vidéo H.264/AVC. Pour la validation fonctionnelle, l ensemble du développement a été réalisé autour d une carte Xilinx à base d un circuit programmable FPGA Xilinx Virtex-5en mettant en œuvre le processeur hardcore PowerPC du circuit programmable dans l environnement logiciel Linux pour l embarqué. Le décodeur H.264/AVC ainsi développé comporte différents accélérateurs matériels pour la transformation inverse ainsi que le filtre anti-blocs. Nous avons pu tester les performances au regard du respect des contraintes temporelles en intégrant une extension temps réel à la plateforme de validation suivant différentes conditions de stress du système. L extension temps réel Xenomai fournit ainsi une réponse adéquate aux problématiques de charge du système et de maîtrise des contraintes temporelles inhérentes à tout système de traitement vidéo tout en autorisant aussi l utilisation d applications classiques mises en œuvre dans l environnement standard Linux embarqué.The main contribution of this thesis concerns the development and the design of an embedded system for multimedia based on the codesign approach (HW/SW). Towards this end, a library off lexible IP cores (Intellectual Property) for video applications was created. In this context, a hardware platform was used for evaluation of the codesign-based approach in order to study video processingalgorithms. Thus, we particularly focused on the study and the implementation of H.264/AVC decoder. For functional validation, the entire development was carried out around a FPGA Virtex-5 Xilinx board embedding a hardcore PowerPC processor running embedded Linux operating system. The H.264/AVC developed decoder consists of hardware accelerators for the inverse transformation and the deblocking filter. We evaluated the performances in terms of respect of temporal constraints by integrating a real-time extension to the validation platform under different stress conditions. The Xenomai real-time extension has proven its high performance level of compliance with hard real-time constraints. This extension offers a real solution for real-time behavior without limiting the use of conventional applications implemented traditionally in a time sharing environment.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

HW/SW Codesign of the H. 263 Video Coder

International audienceIn this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT).Remaining parts were realized in software with NIOS II softcore processor. H.263 coder (NIOS II processor, DCT core) has described by the VHDL language and implemented in Stratix EP1S10 FPGA. Finally, the coder has been tested on the Altera Stratix development board