Electric‐field dependence of interband transitions in In_(0.53)Ga_(0.47)As/In_(0.52)Al_(0.48)As single quantum wells by room‐temperature electrotransmittance

Room‐temperature electrotransmittance has been used in order to investigate the interband excitonic transitions in a 250‐Å‐thick In_(0.53)Ga_(0.47)As/In_(0.52)Al_(0.48)As single‐quantum‐well system as a function of an externally applied electric field. Parity forbidden transitions, involving conduction‐band states with quantum numbers up to n=5, which become more pronounced at high electric fields were observed. The ground‐state and the forbidden transitions showed a significant red shift due to the quantum confined Stark effect. A comparison with previously reported results on thinner InGaAs/InAlAs quantum wells indicated that the wide‐well sample exhibits the largest shift, as expected from theory. Despite the appreciable Stark shift, the rather large, field‐induced linewidth broadening and the relatively low electric field at which the ground‐state exciton is ionized poses limitations on using this wide‐quantum‐well system for electro‐optic applications

High Power Self-Aligned, Trench-Implanted 4H-SiC JFETs

The process technology for the fabrication of 4H-SiC trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) has been developed. The optimized TIVJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. A source-pillars sidewall oxidation and subsequent removal of the metallization from the top of the sidewall oxide ensured isolation between gate and source. Optimum planarization of the source pillars top has been performed by cyclotene spin coating and etch back. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The voltage blocking exhibits a triode shape, which is typical for a static-induction transistor (SIT) operation. The transistors exhibited high ON current handling capabilities (Direct Current density >1kA/cm2) and values of RON ranging from 6 - 12 mΩ•cm2 depending on the channel length. Maximum voltage blocking was 800V limited by the edge termination. The maximum voltage gain was 51. Most transistors were normally-on. Normally-off operation has been observed for transistors lower than 2μm channel width (mask level) and deep implantation