47 research outputs found

    Analysis of Power-aware Buffering Schemes in Wireless Sensor Networks

    Full text link
    We study the power-aware buffering problem in battery-powered sensor networks, focusing on the fixed-size and fixed-interval buffering schemes. The main motivation is to address the yet poorly understood size variation-induced effect on power-aware buffering schemes. Our theoretical analysis elucidates the fundamental differences between the fixed-size and fixed-interval buffering schemes in the presence of data size variation. It shows that data size variation has detrimental effects on the power expenditure of the fixed-size buffering in general, and reveals that the size variation induced effects can be either mitigated by a positive skewness or promoted by a negative skewness in size distribution. By contrast, the fixed-interval buffering scheme has an obvious advantage of being eminently immune to the data-size variation. Hence the fixed-interval buffering scheme is a risk-averse strategy for its robustness in a variety of operational environments. In addition, based on the fixed-interval buffering scheme, we establish the power consumption relationship between child nodes and parent node in a static data collection tree, and give an in-depth analysis of the impact of child bandwidth distribution on parent's power consumption. This study is of practical significance: it sheds new light on the relationship among power consumption of buffering schemes, power parameters of radio module and memory bank, data arrival rate and data size variation, thereby providing well-informed guidance in determining an optimal buffer size (interval) to maximize the operational lifespan of sensor networks

    Application-Level Energy Awareness for OpenMP

    Get PDF

    Challenging complications of hydatid disease

    No full text
    Bu çalışma, 24-28 Mayıs 1999 tarihleri arasında Budapeşte[Macaristan]'de düzenlenen 3. European Congress of the International Hepato-Pacreato-Biliary-Association'da bildiri olarak sunulmuştur.242 patients with hydatid disease were operated on between 1988 and 1998. There were 144 female (59.5%) and 98 male (40.5%) aged 16 to 83 years (mean 42 years) Pain, chills, malaise, jaundice and fever were the other major symptoms on admissions The localisation of 149 single cysts (61.6%) was in right lobe, 57 single cysts (23.6%) in left lobe, 14 multiple cysts (5.7%) in both lobes. and 22 multiple cysts (9.0%) both in liver and in other parenchymal organs, in tissues and in abdominal cavity. Thirty eight cases (15.7%) were recurrent hydatidoses. The treatement procedures that applied to the cysts were partial cystectomy-drainage in 204 cases (83.3%), total cystectomy in 23 cases (9.5%), liver resection in 7 cases (2.9). and percutaneous drainage in 8 cases (3.3%). Serious problems due to sudden ruptures. cysto-biliary connections and recurrences are the most challenging complications of the disease.Int Hepato Pancreato Biliary Asso

    EECache

    No full text

    Circuit and microarchitectural techniques for reducing cache leakage power

    No full text

    Reducing cache misses through programmable decoders

    No full text

    The State of ESL Design

    No full text
    This is the first of two roundtables on electronic system-level design in this issue of IEEE Design & Test. ESL design and tools have been present in the design landscape for many years. Significant ESL innovations are now part of most advanced design methodologies, spanning the domains of modeling, simulation, and synthesis. Techniques such as transaction-level modeling, automatic interconnection generation, behavioral synthesis, automatic instruction-set customization, retargetable compilers, and many others are currently used in the design of multimillion-gate chips. Yet, ESL design still seems to struggle to live up to the promise of providing increased productivity and design quality. This roundtable examines these issues and attempts to provide a definite picture of where ESL design is today and where it might be in the next five to 10 years. The participants in this roundtable include well-known experts in ESL design from the user side, universities, and tool providers. IEEE Design & Test thanks the roundtable participants: moderator Reinaldo Bergamaschi (CadComponents), Luca Benini (University of Bologna), Krisztian Flautner (ARM UK), Wido Kruijtzer (NXP Semiconductors), Alberto Sangiovanni-Vincentelli (University of California, Berkeley), and Kazutoshi Wakabayashi (NEC Japan). D&T gratefully acknowledges the help of Roundtables Editor Bill Joyner (Semiconductor Research Corp.), who organized the event
    corecore