Hierarchical Cluster-Based FIFO Asynchronous Data Transfer Technique for Reducing Congestion for Energy Efficient State Wireless Sensor Network-HAEEW

The applications of WSN can be quiet numerous. In applications like battlefield monitoring, grid power generation, health systems, sensors are deployed on large scale. During such deployment, energy efficiency must be proficient, which requires clustering, in the WSN architecture. Clustering architecture requires maintenance of sensor nodes due to alfunctioning of sensor which becomes depleted of energy. As some nodes leaves and some are being replaced, congestion is introduced in the network due the limited processing capability of memory, computations, and bandwidth condition. This paper proposes one of the energy efficient clustering techniques (HAEEW), using asynchronous data transfer (ADT), which has been modeled from data transfer technique (EEHCR), and using hierarchical clustering. Our model uses synchronization in clock time queries in one and each iterations round time, to determine cluster head, and head-set member formation, using Ad hoc on-demand energy aware routing protocols (AOERP) to make decision. In each iteration, the head-set members receives message request from neighboring nodes to confirm their average distance estimation, in which to transmit aggregated data to the base station. In a sensor deployment, which is aimed for data collection, control and management of sensor nodes, play a vital role, where nodes can be adjusted to boost energy in the network life time. We used matlab for simulations analysis of our result

Real-Time Detection of DoS Attacks in IEEE 802.11p Using Fog Computing for a Secure Intelligent Vehicular Network

The vehicular ad hoc network (VANET) is a method through which Intelligent Transportation Systems (ITS) have become important for the benefit of daily life. Real-time detection of all forms of attacks, including hybrid DoS attacks in IEEE 802.11p, has become an urgent issue for VANET. This is due to sporadic real-time exchange of safety and road emergency message delivery in VANET. Sporadic communication in VANET has the tendency to generate an enormous amount of messages. This leads to overutilization of the road side unit (RSU) or the central processing unit (CPU) for computation. Therefore, efficient storage and intelligent VANET infrastructure architecture (VIA), which includes trustworthiness, are required. Vehicular Cloud and Fog Computing (VFC) play an important role in efficient storage, computation, and communication needs for VANET. This research utilizes VFC integration with hybrid optimization algorithms (OAs), which also possess swarm intelligence, including Cuckoo/CSA Artificial Bee Colony (ABC) and Firefly/Genetic Algorithm (GA), to provide real-time detection of DoS attacks in IEEE 802.11p, using VFC for a secure intelligent vehicular network. Vehicles move ar a certain speed and the data is transmitted at 30 Mbps. Firefly Feed forward back propagation neural network (FFBPNN) is used as a classifier to distinguish between the attacked vehicles and the genuine vehicles. The proposed scheme is compared with Cuckoo/CSA ABC and Firefly GA by considering jitter, throughput, and prediction accuracy.http://dx.doi.org/10.3390/electronics807077

Secure Intelligent Vehicular Network Using Fog Computing

VANET (vehicular ad hoc network) has a main objective to improve driver safety and traffic efficiency. The intermittent exchange of real-time safety message delivery in VANET has become an urgent concern due to DoS (denial of service) and smart and normal intrusions (SNI) attacks. The intermittent communication of VANET generates huge amount of data which requires typical storage and intelligence infrastructure. Fog computing (FC) plays an important role in storage, computation, and communication needs. In this research, fog computing (FC) integrates with hybrid optimization algorithms (OAs) including the Cuckoo search algorithm (CSA), firefly algorithm (FA), firefly neural network, and the key distribution establishment (KDE) for authenticating both the network level and the node level against all attacks for trustworthiness in VANET. The proposed scheme is termed “Secure Intelligent Vehicular Network using fog computing” (SIVNFC). A feedforward back propagation neural network (FFBP-NN), also termed the firefly neural, is used as a classifier to distinguish between the attacking vehicles and genuine vehicles. The SIVNFC scheme is compared with the Cuckoo, the FA, and the firefly neural network to evaluate the quality of services (QoS) parameters such as jitter and throughput.http://dx.doi.org/10.3390/electronics804045

Formal synthesis of VLSI layouts from algorithmic specifications

Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of translating the abstract behavioural representation. In this paper we present a formal approach for high level synthesis. This formal high level syntesis system uses recursive algorithms to model the behaviour to be synthesized. These algorithms can be mathematically verified for correctness before begin subjected to the task of translation. As a case study, the modelling and synthesis of VLSI layouts for matrix-matrix multipliers is discussed. Keywords: Formal synthesis, VLSI layous, Algorithmic specifications, high level synthesi

Building robust prediction models for defective sensor data using Artificial Neural Networks

Predicting the health of components in complex dynamic systems such as an automobile poses numerous challenges. The primary aim of such predictive systems is to use the high-dimensional data acquired from different sensors and predict the state-of-health of a particular component, e.g., brake pad. The classical approach involves selecting a smaller set of relevant sensor signals using feature selection and using them to train a machine learning algorithm. However, this fails to address two prominent problems: (1) sensors are susceptible to failure when exposed to extreme conditions over a long periods of time; (2) sensors are electrical devices that can be affected by noise or electrical interference. Using the failed and noisy sensor signals as inputs largely reduce the prediction accuracy. To tackle this problem, it is advantageous to use the information from all sensor signals, so that the failure of one sensor can be compensated by another. In this work, we propose an Artificial Neural Network (ANN) based framework to exploit the information from a large number of signals. Secondly, our framework introduces a data augmentation approach to perform accurate predictions in spite of noisy signals. The plausibility of our framework is validated on real life industrial application from Robert Bosch GmbH.Comment: 16 pages, 7 figures. Currently under review. This research has obtained funding from the Electronic Components and Systems for European Leadership (ECSEL) Joint Undertaking, the framework programme for research and innovation Horizon 2020 (2014-2020) under grant agreement number 662189-MANTIS-2014-

An efficient multi-time step FEM–SFEM iterative coupling procedure for elastic–acoustic interaction problems

An iterative coupling methodology between the Finite Element Method (FEM) and the Spectral Finite Element Method (SFEM) for the modeling of coupled elastic-acoustic problems in the time domain is presented here. Since the iterative coupling procedure allows the use of a nonconforming mesh at the interface between the subdomains, the difference in the element sizes concerning the FEM and SFEM is handled in a straightforward and efficient manner, thereby retaining all the advantages of the SFEM. By means of the HHT time integration method, controllable numerical damping can be introduced in one of the subdomains, increasing the robustness of the method and improving the accuracy of the results; besides, independent time-step sizes can be considered within each subdomain, resulting in a more efficient algorithm. In this work, a modification in the subcycling procedure is proposed, ensuring not only an efficient and accurate methodology but also avoiding the computation of a relaxation parameter. Numerical simulations are presented in order to illustrate the accuracy and potential of the proposed methodology.CAPES, UFJF, UFSJ, FAPEMIG and CNP

Design of a Cell Library for Formal High-level Synthesis

In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the Realization Specification Language (RSL) [1] as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplayer is presented to illustrate the application of the cell library

Formal synthesis of VLSI layouts from algorithmic specifications

Due to advances in VLSI technology, it is possible to implement complex digital systems on a single chip. However modeling such large and complex at structural level is tedious and error prone. This fact has motivated the development of several high-level synthesis systems. The process consists of translating the abstract behavioural representation. In this paper we present a formal approach for high level synthesis. This formal high level syntesis system uses recursive algorithms to model the behaviour to be synthesized. These algorithms can be mathematically verified for correctness before begin subjected to the task of translation. As a case study, the modelling and synthesis of VLSI layouts for matrix-matrix multipliers is discussed. Keywords: Formal synthesis, VLSI layous, Algorithmic specifications, high level synthesi