UC-31 An Empirical Study of Thermal Attacks on Edge Platforms

Cloud-edge systems are vulnerable to thermal attacks as the increased energy consumption may remain undetected, while occurring alongside normal, CPU-intensive applications. The purpose of our research is to study thermal effects on modern edge systems. We also analyze how performance is affected from the increased heat and identify preventative measures. We speculate that due to the technology being a recent innovation, research on cloud-edge devices and thermal attacks is scarce. Other research focuses on server systems rather than edge platforms. In our paper, we use a Raspberry Pi 4 and a CPU-intensive application to represent thermal attacks on cloud-edge systems. We performed several experiments with the Raspberry Pi 4 and used stress-ng, a benchmarking tool available on Linux distributions, to simulate the attacks. The resulting effects displayed drastic increases in the temperature and power consumption. The key impact of our research is to highlight the following risks and mitigation plans: the vulnerability of cloud-edge systems from thermal attacks, the capability for the attacks to go unnoticed, to further the understanding of edge devices as well as the prevention of these attacks.Advisors(s): Dr. Kun SuoTopic(s): Securit

Chemical functionalisation of silicon and germanium nanowires

The reduced dimensionality of nanowires implies that surface effects significantly influence their properties, which has important implications for the fabrication of nanodevices such as field effect transistors and sensors. This review will explore the strategies available for wet chemical functionalisation of silicon (Si) and germanium (Ge) nanowires. The stability and electrical properties of surface modified Si and Ge nanowires is explored. While this review will focus primarily on nanowire surfaces, much has been learned from work on planar substrates and differences between 2D and nanowire surfaces will be high-lighted. The possibility of band gap engineering and controlling electronic characteristics through surface modification provides new opportunities for future nanowire based applications. Nano-sensing is emerging as a major application of modified Si nanowires and the progress of these devices to date is discussed

AuxAg1-x alloy seeds: A way to control growth, morphology and defect formation in Ge nanowires

Germanium (Ge) nanowires are of current research interest for high speed nanoelectronic devices due to the lower band gap and high carrier mobility compatible with high K-dielectrics and larger excitonic Bohr radius ensuing a more pronounced quantum confinement effect [1-6]. A general way for the growth of Ge nanowires is to use liquid or a solid growth promoters in a bottom-up approach which allow control of the aspect ratio, diameter, and structure of 1D crystals via external parameters, such as precursor feedstock, temperature, operating pressure, precursor flow rate etc [3, 7-11]. The Solid-phase seeding is preferred for more control processing of the nanomaterials and potential suppression of the unintentional incorporation of high dopant concentrations in semiconductor nanowires and unrequired compositional tailing of the seed-nanowire interface [2, 5, 9, 12]. There are therefore distinct features of the solid phase seeding mechanism that potentially offer opportunities for the controlled processing of nanomaterials with new physical properties. A superior control over the growth kinetics of nanowires could be achieved by controlling the inherent growth constraints instead of external parameters which always account for instrumental inaccuracy. The high dopant concentrations in semiconductor nanowires can result from unintentional incorporation of atoms from the metal seed material, as described for the Al catalyzed VLS growth of Si nanowires [13] which can in turn be depressed by solid-phase seeding. In addition, the creation of very sharp interfaces between group IV semiconductor segments has been achieved by solid seeds [14], whereas the traditionally used liquid Au particles often leads to compositional tailing of the interface [15] . Korgel et al. also described the superior size retention of metal seeds in a SFSS nanowire growth process, when compared to a SFLS process using Au colloids [12]. Here in this work we have used silver and alloy seed particle with different compositions to manipulate the growth of nanowires in sub-eutectic regime. The solid seeding approach also gives an opportunity to influence the crystallinity of the nanowires independent of the substrate. Taking advantage of the readily formation of stacking faults in metal nanoparticles, lamellar twins in nanowires could be formed

Higher Nerves of Simplicial Complexes

We investigate generalized notions of the nerve complex for the facets of a simplicial complex. We show that the homologies of these higher nerve complexes determine the depth of the Stanley-Reisner ring $k[\Delta]$ as well as the $f$-vector and $h$-vector of $\Delta$. We present, as an application, a formula for computing regularity of monomial ideals.Comment: We rewrite Section 4 to fix some errors and clarify the proof

Ferroelectric nanoparticles, wires and tubes: synthesis, characterisation and applications

Nanostructured materials are central to the evolution of future electronics and information technologies. Ferroelectrics have already been established as a dominant branch in the electronics sector because of their diverse application range such as ferroelectric memories, ferroelectric tunnel junctions, etc. The on-going dimensional downscaling of materials to allow packing of increased numbers of components onto integrated circuits provides the momentum for the evolution of nanostructured ferroelectric materials and devices. Nanoscaling of ferroelectric materials can result in a modification of their functionality, such as phase transition temperature or Curie temperature (TC), domain dynamics, dielectric constant, coercive field, spontaneous polarisation and piezoelectric response. Furthermore, nanoscaling can be used to form high density arrays of monodomain ferroelectric nanostructures, which is desirable for the miniaturisation of memory devices. This review article highlights some research breakthroughs in the fabrication, characterisation and applications of nanoscale ferroelectric materials over the last decade, with priority given to novel synthetic strategies

Engineering metallic nanoparticles for enhancing and probing catalytic reactions

Recent developments in tailoring the structural and chemical properties of colloidal metal nanoparticles (NPs) have led to significant enhancements in catalyst performance. Controllable colloidal synthesis has also allowed tailor-made NPs to serve as mechanistic probes for catalytic processes. The innovative use of colloidal NPs to gain fundamental insights into catalytic function will be highlighted across a variety of catalytic and electrocatalytic applications. The engineering of future heterogenous catalysts is also moving beyond size, shape and composition considerations. Advancements in understanding structure-property relationships have enabled incorporation of complex features such as tuning surface strain to influence the behavior of catalytic NPs. Exploiting plasmonic properties and altering colloidal surface chemistry through functionalization are also emerging as important areas for rational design of catalytic NPs. This news article will highlight the key developments and challenges to the future design of catalytic NPs

Inducing imperfections in germanium nanowires

Nanowires with inhomogeneous heterostructures such as polytypes and periodic twin boundaries are interesting due to their potential use as components for optical, electrical, and thermophysical applications. Additionally, the incorporation of metal impurities in semiconductor nanowires could substantially alter their electronic and optical properties. In this highlight article, we review our recent progress and understanding in the deliberate induction of imperfections, in terms of both twin boundaries and additional impurities in germanium nanowires for new/enhanced functionalities. The role of catalysts and catalyst–nanowire interfaces for the growth of engineered nanowires via a three-phase paradigm is explored. Three-phase bottom-up growth is a feasible way to incorporate and engineer imperfections such as crystal defects and impurities in semiconductor nanowires via catalyst and/or interfacial manipulation. “Epitaxial defect transfer” process and catalyst–nanowire interfacial engineering are employed to induce twin defects parallel and perpendicular to the nanowire growth axis. By inducing and manipulating twin boundaries in the metal catalysts, twin formation and density are controlled in Ge nanowires. The formation of Ge polytypes is also observed in nanowires for the growth of highly dense lateral twin boundaries. Additionally, metal impurity in the form of Sn is injected and engineered via third-party metal catalysts resulting in above-equilibrium incorporation of Sn adatoms in Ge nanowires. Sn impurities are precipitated into Ge bi-layers during Ge nanowire growth, where the impurity Sn atoms become trapped with the deposition of successive layers, thus giving an extraordinary Sn content (>6 at.%) in Ge nanowires. A larger amount of Sn impingement (>9 at.%) is further encouraged by utilizing the eutectic solubility of Sn in Ge along with impurity trapping