896 research outputs found

    Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

    Get PDF
    In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSEETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSEETs have better on-state currents than do the FinFETs because of larger effective widths (W-eff) under the same device area. Particularly p-type NSEETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSEETs have larger gate capacitances because larger W-eff increase the gate-to-source/drain overlap and outer-fringing capacitances. In spite of that, sub-7-nm node NSEETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.11Ysciescopu

    Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

    Get PDF
    Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the first time. It is challenging to scale down conventional bulk FinFETs into 5-nm technology node due to the sub-fin leakage increase. Meanwhile, bottom oxide deposition after anisotropic etching for source/drain (S/D) epi formation prevents the sub-fin leakage effectively even without the PTS doping, thus achieving better gate-to-channel controllability. Bottom oxide FinFETs also have smaller gate capacitances than do conventional FinFETs because the parasitic capacitances decrease by smaller S/D epi separated from the bottom Si layer, which reduces junction and outer-fringing capacitances. But smaller S/D epi decreases the stresses along the channel direction, and the effective widths decrease by the bottom oxide layer blocking the current paths at the bottom side of fin channels. Furthermore, increase of the interconnect resistance and capacitance parasitics down to 5-nm node diminishes the improvements of total delays as the interconnect wire length increases greatly. In spite of these drawbacks, 5-nm node bottom oxide FinFETs achieve smaller total delays than do the 7-nm node conventional FinFETs, especially for low-power applications, thus promising for the scalability of bulk FinFETs along with simple and reliable process by avoiding PTS step.11Ysciescopu

    Temperature dependence of Mott transition in VO_2 and programmable critical temperature sensor

    Full text link
    The temperature dependence of the Mott metal-insulator transition (MIT) is studied with a VO_2-based two-terminal device. When a constant voltage is applied to the device, an abrupt current jump is observed with temperature. With increasing applied voltages, the transition temperature of the MIT current jump decreases. We find a monoclinic and electronically correlated metal (MCM) phase between the abrupt current jump and the structural phase transition (SPT). After the transition from insulator to metal, a linear increase in current (or conductivity) is shown with temperature until the current becomes a constant maximum value above T_{SPT}=68^oC. The SPT is confirmed by micro-Raman spectroscopy measurements. Optical microscopy analysis reveals the absence of the local current path in micro scale in the VO_2 device. The current uniformly flows throughout the surface of the VO_2 film when the MIT occurs. This device can be used as a programmable critical temperature sensor.Comment: 4 pages, 3 figure

    Whole-brain imaging with receive-only multichannel top-hat dipole antenna RF coil at 7 T MRI

    Get PDF
    This work investigates the construction and performance of an eight-channel top-hat dipole receiver RF coil with a capacitive plate to increase the longitudinal whole-brain coverage and receiver sensitivity gain in the brain at 7 T MRI. The construction method for top-hat dipole-based receiver RF coil by adjusting the length and structure corresponding to each channel consists of tuning, matching, balun, and detuning circuitry. Electromagnetic simulations were analyzed on a 3-D human model to evaluate B1+ efficiency and specific absorption rate deposition. Coil performance was evaluated in the human head imaging in vivo. EM simulation results indicated a higher B1− sensitivity in the brain and z-directional coverage of the proposed eight-channel receiver RF coil. The MR images were acquired with an identical field of view showing the receiver coverage improvement in the brain when capacitive plates are used. The MR images also show the clear visibility of the complete set of the cervical vertebrae as well as the spinal cord. The acquired MRI results demonstrate the capability of the proposed RF coil to increase the receiver coverage in the longitudinal direction. Moreover, the B1+ efficiency, as well as receiver sensitivity in the brain, can be substantially improved with the use of multilayered capacitive plates of proper shape and size in conjunction with an RF coil

    Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

    Get PDF
    A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.11Ysciescopu

    Time Pattern Locking Scheme for Secure Multimedia Contents in Human-Centric Device

    Get PDF
    Among the various smart multimedia devices, multimedia smartphones have become the most widespread due to their convenient portability and real-time information sharing, as well as various other built-in features. Accordingly, since personal and business activities can be carried out using multimedia smartphones without restrictions based on time and location, people have more leisure time and convenience than ever. However, problems such as loss, theft, and information leakage because of convenient portability have also increased proportionally. As a result, most multimedia smartphones are equipped with various built-in locking features. Pattern lock, personal identification numbers, and passwords are the most used locking features on current smartphones, but these are vulnerable to shoulder surfing and smudge attacks, allowing malicious users to bypass the security feature easily. In particular, the smudge attack technique is a convenient way to unlock multimedia smartphones after they have been stolen. In this paper, we propose the secure locking screen using time pattern (SLSTP) focusing on improved security and convenience for users to support human-centric multimedia device completely. The SLSTP can provide a simple interface to users and reduce the risk factors pertaining to security leakage to malicious third parties
    corecore