Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and faulttolerance into these devices. Moreover, fault tolerant properties of multi- layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 µm CMOS technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built

A cell-electrode interface noise model for high-density microelectrode arrays

A cell-electrode interface noise model is developed which is dedicated to enable the co-simulation of the cell-electrode electrical characteristics, along with the electronics of novel CMOS-based MEA. The electrode noise is investigated for Pt and Pt black electrodes. It is shown that the electrode noise can be the dominant noise source in the full system. Moreover, Pt black electrodes benefit from up to 5 µVrms decrease of the electrode output noise, for small electrodes. Furthermore, the cell-electrode interface noise spectral density is shown to be 10 dB to 20 dB larger at 1 kHz when a cell is lying on top of the electrode. This increase depends on the neural cell adhesion on the MEA surface

Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays

Accurate electrical models are needed to support the design of modern microelectrode arrays. The point-contact model is presented thoroughly, and an area-contact model is analytically derived in order to model the electrical characteristics of the cell-electrode interface at subcellular resolution. An optimum electrode diameter for recording the electrical activity of neurons is analytically determined at 8 um, with a cell diameter of 10 um and a typical load capacitance of 10 pF. Finally, three- dimensional tip electrodes are characterized using the area- contact model. An improvement of the electrical coupling up to 20 dB is observed for small electrodes, in simulation

An Electrical Model of the Cell-Electrode Interface for High-density Microelectrode Arrays

A point-contact model is presented, and an areacontact model has been analytically derived in order to model the electrical characteristic of the cell-electrode interface of high-density neuron cultures. The area-contact model is presented as a model more suitable for subcellular multielectrode resolution, which is a requisite for modeling and simulating the electrical behavior of novel high-density microelectrode arrays. Furthermore, when the electrode is aligned and centered with the cell, an optimum electrode diameter for recording the electrical activity of neural cells can be analytically derived, which is between 7-8 µm with a typical load capacitance of 10 pF

Three-dimensional Tip Electrode Array Technology for High Resolution Neuro-Electronic Systems used in Electrophysiological Experiments in-vitro

A three-dimensional tip electrode array technology for in-vitro electrophysiological experiments is presented. Based on simulation results obtained with a finite element model of the neuron-electrode interface, it has been shown that the electrical coupling between the neural cells and the three-dimensional tip electrode array is improved compared to standard planar electrodes. Consequently, three-dimensional microelectrode arrays (MEAs) exhibiting a higher spatial resolution than classical integrated MEA systems have been manufactured using the proposed fabrication process. Three-dimensional tip electrode arrays with an electrode diameter of 3-4µm, a height of 1.75µm, and a pitch dimension of 5-6µm have been manufactured on silicon substrate. Future in-vitro electrophysiological experiments are expected to confirm the superiority of the three-dimensional electrodes over the planar electrodes

Neuro-Electronic Interfacing Methods for High-Density CMOS-Compatible Microelectrode Arrays

Recently, CMOS-based microelectrode arrays containing a high-density of electrodes have emerged as a tool enabling recording the extracellular neural electrical activity of cell cultures at subcellular resolution. However, several improvements in areas such as the low-noise front-end readout electronics, post CMOS fabrication processing of the electrode array, or the cell-electronics co-simulation are still required in order to enable the widespread use of high-density active MEAs. An electrical model of the cell-electrode interface characteristics has been developed, enabling co-simulation of the cell-electrode environment with the front-end electronics at subcellular resolution. This model has shown to be adapted to determine the optimum electrode size, the amplitude of the sensed voltage, and the noise injected by the cell-electrode interface. Moreover, simulations performed using this model has also shown that the electrical coupling between a neural cell and an individual sensor is improved in the case of three-dimensional electrodes. Compared to planar electrodes, a 10-20 dB increase of the electrical coupling is observed for subcellular resolution three-dimensional tip electrodes, in simulation. The fabrication of high-density three-dimensional tip electrode array has thus been investigated. A novel post-processing technique which enables the systematic fabrication of very dense floating-gate field-effect transistor (FG-FET) arrays is presented. Several three-dimensional microstructures such as pillar, pyramidal, and inverted pyramidal microstructures have been manufactured. A maximum sensor density of 295'200 sensors/mm2, which corresponds to a sensor pitch dimension of 1.84 µm, has been obtained with pillar structures. Moreover, since no photolithographic steps are necessary for manufacturing the high-density FG-FET arrays, it has been shown that the proposed manufacturing technique is adapted in the case where die-level postprocessing is performed. An innovative readout architecture, where a single amplification stage simultaneously records the activity acquired from several electrodes, has also been developed. This new readout method, based on the amplitude modulation of the recorded signals, enables the design of a low-noise amplification stage while still reading the extracellular activity sensed by the whole electrode array. A theoretical analysis has demonstrated that a major physical limitation of the proposed readout architecture relates to the summation of the thermal noise of each recorded signal at the input node of the front-end amplification stage. After CMOS implementation of the proposed readout architecture, it has been shown that the maximum number of sensors which can simultaneously be recorded depends on the electrical characteristics of the recorded extracellular voltages, which depend on the experimental setup. If a typical case encountered during electrophysiological experiments is considered, the maximum number of electrodes which can be simultaneously recorded is approximately in the range of 5-10

Extracellular recording system based on amplitude modulation for CMOS microelectrode arrays

An innovative readout channel, based on analog amplitude modulation of the signals recorded by each sensing site, is developed for high-density CMOS-based microelectrode arrays. A single amplification stage simultaneously records the neural activity acquired from several sensors. A theoretical analysis has demonstrated that a major physical limitation of the readout architecture relates to the summation of the thermal noise of each recorded signal at the input node of the front-end amplification stage. After implementation of the proposed readout architecture in a UMC 0.18 um CMOS technology, it has been shown that the maximum number of sensors which can simultaneously be recorded depends on the electrical characteristics of the recorded extracellular voltages, which depend on the experimental setup. Considering a typical case encountered during electrophysiological experiments, the maximum number of sensors which can simultaneously be recorded is approximately in the range of 5-10

Matrice de micro électrodes à haute résolution spatiale pour la mesure du potentiel extracellulaire des cellules nerveuses

Une nouvelle approche basée sur des électrodes en 3D a été développée afin d’accroître le couplage électrique entre les cellules nerveuses et les capteurs d’une matrice de micro électrodes (MEA). Cette amélioration du couplage électrique obtenue par des matrices d’électrodes en 3D par rapport à des électrodes planaires standards a été confirmée par simulation. Des MEAs 3D ayant une meilleure résolution spatiale ont été fabriquées sur des plaquettes de Silicium