Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area

Viscous Dissipative Flow between Parallel Plates

Increasing degree of miniaturization in devices has led to studies in micro-scale heat and fluid flow, since the thermal behaviour in small devices and in micro-channels may deviate substantially from that of large objects. One of the effects that could play an important role in mirror-channels is the viscous dissipation effect, and described by the Brinkman number. Initially, basic analytical expressions for Nusselt number with the effect of viscous dissipation on the heat transfer between infinite fixed parallel plates, where the focus is on-dynamically and thermally fully developed flow of a Newtonian fluid with constant properties, neglecting the axial heat conduction has been analysed. Thermal boundary conditions considered are: both the plates kept at different constant heat fluxes, both the plates kept at equal constant heat fluxes, and one plate insulted. From the analysis, new expressions for Nusselt numbers have been found, as a function of various definitions of the Brinkman number

Effects of single vegetation obstruction on 5G mobile services in 28GHz

Vegetative medium causes the attenuation of radio frequency waves, whereby the attenuation increases with frequency. Fifth Generation bands will operate in very high frequencies, thus creating an emphasis to study the vegetative propagation properties of these signals. Different species of trees can cause a variation in propagation loss due to the difference of the tree crown shapes. Existing vegetation loss modelling does not take into account the effects of tree crown shape. Therefore, prediction result does not reflect the accurate amount of signal attenuation experienced by trees. An underestimation of the signal attenuation can cause bad link budget designing. This paper shows that the peak attenuation for hemispherical and spherical crown of common tree species found in Kuala Lumpur, Malaysia is 7.59 % and 3.83% different from the predicted signal attenuation with a fixed vegetation volume of 27m3. This paper suggests that existing vegetation modelling requires some adjustment before it can be applied for the assumption of vegetation attenuation when designing an RF link in very high frequency bands, especially in equatorial climate

Design A Low Power And High Throughput Error Detection And Data Correction Architecture By Razor II Method

The proposed error detection and correction circuit designed due to the existing circuits accommodate the worst-case delay. To prevent Error in the system, detect and determine violation to maintain correctness to help on the fly mechanisms. The proposed circuit is to present speculative error detection technique along with an error recovery mechanism. Circuits are wanted to oblige the delay and to get to be deficient in their execution. To enhance the execution, they oblige fly system to forestall, identify and correct errors. In this paper, low power speculative error detection and error recovery architecture are PJAEE, 17 (9) (2020) 4394 to be developed. The main aim of the circuit is to reduce delay, power and area. This paper demonstrates their ability to operate under worst-case accommodation. The proposed error correction and detection circuit give 226nW, propagation delay 1ps, throughput 792MHz.

Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area

3-dB Branch-line coupler using coupled line radial stub with no restriction on coupling power

Investigation on the design of coupled line radial stub towards 3-dB branch-line coupler (BLC) operating for fourth generation (4G) Long Term Evolution (LTE) at 3.5 GHz has been presented in this paper. The investigation involves different parameter value of the radius of radial stub and coupled line length at the series and shunt arm of 3-dB BLC designs specifically without restriction on the coupling power performance. The designed BLC was simulated using Rogers RO4003C substrate with thickness of 0.508 mm and dielectric constant of 3.38. The results for proposed radial stub BLC were being compared in terms of S-parameter and phase difference. The comparison shows that 3-dB BLC with radial shaped stub optimized to 79% reduction compared to conventional design without having to compromise the performance result especially with no restriction on the coupling power