Novel active-compensated weighted summer

A summer amplifier with extended bandwidth is proposed. Compensation of the frequency characteristics is achieved by employing two operational amplifiers instead of external reactive components

On the Active Compensation of Operational Amplifier Based VCVS

A unified treatment of the active compensation for VCVS realized by operational amplifiers is presented. It is a summary of low-sensitivity circuit structures which can be either magnitude or phase compensated. The performance of such a circuits is discussed in detail. Experimental data for some of them are also included

A 4-mode reconfigurable low noise amplifier for implantable neural recording channels

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by circuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.Office of Naval Research (USA) N00014-14-1-0355Junta de Andalucía TIC 233

A 2.2 μW analog front-end for multichannel neural recording

In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain amplifier (VGA). The proposed architecture employs highly power-noise efficient current reuse fully differential OTAs in the LNA stage and a fully differential folded cascode for the VGA stage. Simulation results in AMS 0.18μm validate the proposed architecture under process corners variations with an estimated power consumption of 2.2μm and 3.1 μVrms in-band noise.Ministerio de Economía y Competitividad TEC2016- 80923-POffice of Naval Research (USA) N00014111031

Chaos in a Switched-Capacitor Circuit

We report chaotic phenomena observed from a simple nonlinear switched-capacitor circuit. The experimentally measured bifurcation tree diagram reveals a period-doubling route to chaos. This circuit is described by a first-order discrete equation which can be transformed into the logistic map whose chaotic dynamics is well known.National Science Foundation ECS-8542885Comisión Interministerial de Ciencia y Tecnología 0245/81Office of Naval Research under Contract NOOO14-76-C-057

A new nonlinear time-domain op-amp macromodel using threshold functions and digitally controlled network elements

A general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op amps), either bipolar or MOS, is presented. Three main differences exist between the macromodel and those previously reported in the literature for the time domain. First, all the op-amp nonlinearities are simulated using threshold elements and digital components, thus making them well suited for a mixed electrical/logical simulator. Secondly, the macromodel exhibits a superior performance in those cases where the op amp is driven by a large signal. Finally, the macromodel is advantageous in terms of CPU time. Several examples are included illustrating all of these advantages. The main application of this macromodel is for the accurate simulation of the analog part of a combined analog/digital integrated circui

Design of RC-active oscillators using composite amplifiers

The design of composite opamp Wien-Bridge oscillators is systematically approached by using a general model including amplitude control issues. Two different design criteria are presented and their main features summarized. A general composite opamp topology from which a catalog of structures can be obtained in a systematic way is presented. Experimental data are included illustrating the performance of the proposed design criteria

A mixed-signal integrated circuit for FM-DCSK modulation

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER = 10-3 for Eb/No lower than 28 dB.Ministerio de Ciencia y Tecnología TIC2003-0235

New analogue switch circuit having very low forward resistance

A new circuit realisation for an analogue switch is reported. The main feature of the proposed design is the low value of the forward resistance as compared with commercial switches. Experimental data confirming the performance of the circuit are also included