Memory and Parallelism Analysis Using a Platform-Independent Approach

Emerging computing architectures such as near-memory computing (NMC) promise improved performance for applications by reducing the data movement between CPU and memory. However, detecting such applications is not a trivial task. In this ongoing work, we extend the state-of-the-art platform-independent software analysis tool with NMC related metrics such as memory entropy, spatial locality, data-level, and basic-block-level parallelism. These metrics help to identify the applications more suitable for NMC architectures.Comment: 22nd ACM International Workshop on Software and Compilers for Embedded Systems (SCOPES '19), May 201

Reducing the burden of depression in youth: what are the implications of neuroscience and genetics on policies and programs?

Mood disorders are a leading cause of the burden of disease in youth. Three critical lessons emerge from the reviews in this issue that are relevant to our understanding of these common mental disorders: first, that the brain is in a highly dynamic stage of its development during youth; second, that environmental factors interact with genetic factors to influence the probability of risk behaviors and dysphoric states; and third, that shared developmental and genetic factors may account for the bulk of emotional and behavioral outcomes in youth, and that environmental influences may affect the specific expression of the phenotypes associated with these pathways. Although this evidence does not immediately indicate the potential for new interventions, it is consistent with current policy and practice recommendations. Interventions should focus on both improving the early detection and management of depressive disorders as well as preventive strategies that aim to train children and youth to improve cognitive control and manage stress more effectively. Limiting access to harmful risk-taking situations and providing opportunities to engage are less harmful, but equally exciting, alternatives in a pragmatic universal prevention policy option. Key research priorities and paradigms emerge from this evidence, particularly in the context of the grand challenges in global mental health

Ultrasound evaluation of the uterine cesarean section scar

Niches have shown to be quite prevalent and can be visualized by transvaginal ultrasound. With this thesis we added the first practical guidelines on niche evaluation in non-pregnant women and in early pregnancy to detect a cesarean scar pregnancy. They can be used in daily clinical practice and will hopefully establish uniformity in future niche studies and increase awareness for the existence of a cesarean scar pregnancy amongst all sonographers performing ultrasound in early pregnancy after cesarean section. During evaluation, it should be considered that niche presence and features change over time after cesarean section. Niche presence disturbs uterine peristalsis, possibly causing niche-related symptoms and subfertility, but this must be further assessed. Its presence does not appear to be affected by uterine closure technique, although the learning curve of uterine closure does seem important. Laparoscopic niche resection increases the residual myometrial thickness, which is favorable during subsequent pregnancy; future research will have to focus on the improvement of obstetric outcomes by laparoscopic niche resection. As a cesarean section cannot be prevented in obstetric policy, proper counseling of women with or without medical indication for a cesarean section should be part of daily practice, including niche-related symptoms. This should be done before but otherwise during follow-up after the cesarean section. Furthermore, recognizing these symptoms in primary care will lead to a sense of understanding in women and not cause an unnecessary delay in therapeutic management

Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm

Genetic algorithms are commonly used for automatically solving complex design problem because exploration using genetic algorithms can consistently deliver good results when the algorithm is given a long enough run-time. However, the exploration time for problems with huge design spaces can be very long, often making exploration using a genetic algorithm practically infeasible. In this work, we present a genetic algorithm for exploring the instruction-set architecture of VLIW ASIPs and demonstrate its effectiveness by comparing it to two heuristic algorithms. We present several optimizations to the genetic algorithm configuration, and demonstrate how caching of intermediate compilation and simulation results can reduce the exploration time by an order of magnitude

MoviCompile : An LLVM based compiler for heterogeneous SIMD code generation

Numerous applications in communication and multimedia domains show significant data-level parallelism (DLP). The amount of DLP varies between applications in the same domain or even within a single application. Most architectures support a single vector-, SIMD-width which may not be optimal. This may cause performance and energy inefficiency. We propose the use of multiple (heterogeneous) vector-widths to better serve applications with varying DLP. The SHAVE (Streaming Hybrid Architecture Vector Engine) VLIW vector processor shown in Figure 1 is an example of such an architecture. SHAVE is a unique VLIW processor that provides hardware support for native 32-bit (short) and 128-bit (long) vector operations. Vector arithmetic unit (VAU) supports 128-bit vector arithmetic of 8/16/32-bit integer and 16/32-bit floating point types. Scalar arithmetic unit (SAU) supports 32-bit vector arithmetic of 8/16-bit integer and 16-bit floating point types. The moviCompile compiler is an LLVM based commercial compiler targeting code generation for SHAVE processor family. The moviCompile compiler is capable of SIMD code generation for 128-bit (long) and 64-bit vector operations. This work focuses on compiler backend support for 32-bit (short) vector operations. More specifically, this work aims to generate SIMD code for short vector types (e.g. 4 x i8, 2 x i16, 2 x f16) that can be executed on 32-bit SAU next to the 128/64-bit SIMD code. As a result, moviCompile is able to generate heterogeneous assembly code consisting of both short and long vector SIMD operations. Currently, we are testing the compiler using TSVC (Test Suite for Vectorizing Compilers) and intend to measure the performance improvements